mul4_1_case_tb.tf

FPGA开发板上写的Verilog代码 功能是从电脑端发送一个字节

module testbench();

// Inputs
    reg [1:0] s;
    reg [3:0] i;


// Outputs
    wire y;

// Instantiate the UUT
    mul4_1_if uut (
        .y(y), 
        .s(s), 
        .i(i)
        );


// Initialize Inputs
initial
 $monitor ($time,"y=%b, s=%b, i=%b", y, s, i);

initial	//Initialize input signals
 begin
    s = 2'b00;
    i = 4'b0101;
 end

initial 
 begin
   #20  s = 2'b01;   //Set selection at different times
   #20  s = 2'b10;
   #20  s = 2'b11;
 end

initial #100 $finish;  //Complete simulation after 120 time units
  
endmodule