📄 newhour.rpt
字号:
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\wy\newhour.rpt
newhour
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------------- LC21 hour10
| +------------------- LC20 hour11
| | +----------------- LC19 hour12
| | | +--------------- LC18 hour13
| | | | +------------- LC17 hour20
| | | | | +----------- LC22 hour21
| | | | | | +--------- LC23 hour22
| | | | | | | +------- LC24 hour23
| | | | | | | | +----- LC27 |LPM_ADD_SUB:227|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | +--- LC26 |LPM_ADD_SUB:227|addcore:adder|addcore:adder0|result_node2
| | | | | | | | | | +- LC25 |LPM_ADD_SUB:227|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC21 -> * * * * * * * * * * * | - * | <-- hour10
LC20 -> - * * * * * * * * * * | - * | <-- hour11
LC19 -> - * * * * * * * - * * | - * | <-- hour12
LC18 -> - * * * * * * * - - * | - * | <-- hour13
LC17 -> - * * * * * * * - - - | - * | <-- hour20
LC22 -> - * * * * * * * - - - | - * | <-- hour21
LC23 -> - * * * * * * * - - - | - * | <-- hour22
LC24 -> - * * * * * - * - - - | - * | <-- hour23
LC27 -> - * - - - - - - - - - | - * | <-- |LPM_ADD_SUB:227|addcore:adder|addcore:adder0|result_node1
LC26 -> - - * - - - - - - - - | - * | <-- |LPM_ADD_SUB:227|addcore:adder|addcore:adder0|result_node2
LC25 -> - - - * - - - - - - - | - * | <-- |LPM_ADD_SUB:227|addcore:adder|addcore:adder0|result_node3
Pin
43 -> - - - - - - - - - - - | - - | <-- carrym
4 -> * * * * * * * * - - - | - * | <-- reset
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\wy\newhour.rpt
newhour
** EQUATIONS **
carrym : INPUT;
reset : INPUT;
-- Node name is 'hour10' = 'hourt10'
-- Equation name is 'hour10', location is LC021, type is output.
hour10 = TFFE( VCC, GLOBAL( carrym), !reset, VCC, VCC);
-- Node name is 'hour11' = 'hourt11'
-- Equation name is 'hour11', location is LC020, type is output.
hour11 = DFFE( _EQ001 $ _LC027, GLOBAL( carrym), !reset, VCC, VCC);
_EQ001 = hour10 & hour11 & !hour12 & !hour13 & !hour20 & hour21 &
!hour22 & !hour23 & _LC027
# hour10 & !hour11 & !hour12 & hour13 & _LC027;
-- Node name is 'hour12' = 'hourt12'
-- Equation name is 'hour12', location is LC019, type is output.
hour12 = DFFE( _EQ002 $ _LC026, GLOBAL( carrym), !reset, VCC, VCC);
_EQ002 = hour10 & hour11 & !hour12 & !hour13 & !hour20 & hour21 &
!hour22 & !hour23 & _LC026
# hour10 & !hour11 & !hour12 & hour13 & _LC026;
-- Node name is 'hour13' = 'hourt13'
-- Equation name is 'hour13', location is LC018, type is output.
hour13 = DFFE( _EQ003 $ _LC025, GLOBAL( carrym), !reset, VCC, VCC);
_EQ003 = hour10 & hour11 & !hour12 & !hour13 & !hour20 & hour21 &
!hour22 & !hour23 & _LC025
# hour10 & !hour11 & !hour12 & hour13 & _LC025;
-- Node name is 'hour20' = 'hourt20'
-- Equation name is 'hour20', location is LC017, type is output.
hour20 = TFFE( _EQ004, GLOBAL( carrym), !reset, VCC, VCC);
_EQ004 = hour10 & !hour11 & !hour12 & hour13 & !hour20 & hour23
# hour10 & !hour11 & !hour12 & hour13 & !hour20 & hour22
# hour10 & !hour11 & !hour12 & hour13 & !hour20 & !hour21
# hour10 & !hour11 & !hour12 & hour13 & hour20;
-- Node name is 'hour21' = 'hourt21'
-- Equation name is 'hour21', location is LC022, type is output.
hour21 = TFFE( _EQ005, GLOBAL( carrym), !reset, VCC, VCC);
_EQ005 = hour10 & !hour11 & !hour12 & hour13 & !hour20 & hour21 &
!hour22 & !hour23
# hour10 & hour11 & !hour12 & !hour13 & !hour20 & hour21 &
!hour22 & !hour23
# hour10 & !hour11 & !hour12 & hour13 & hour20;
-- Node name is 'hour22' = 'hourt22'
-- Equation name is 'hour22', location is LC023, type is output.
hour22 = TFFE( _EQ006, GLOBAL( carrym), !reset, VCC, VCC);
_EQ006 = hour10 & !hour11 & !hour12 & hour13 & hour20 & hour21;
-- Node name is 'hour23' = 'hourt23'
-- Equation name is 'hour23', location is LC024, type is output.
hour23 = TFFE( _EQ007, GLOBAL( carrym), !reset, VCC, VCC);
_EQ007 = hour10 & !hour11 & !hour12 & hour13 & hour20 & hour21 &
hour22;
-- Node name is '|LPM_ADD_SUB:227|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( hour11 $ hour10);
-- Node name is '|LPM_ADD_SUB:227|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried
_LC026 = LCELL( hour12 $ _EQ008);
_EQ008 = hour10 & hour11;
-- Node name is '|LPM_ADD_SUB:227|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( hour13 $ _EQ009);
_EQ009 = hour10 & hour11 & hour12;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\wy\newhour.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,226K
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