vga_system.tan.rpt

verilog代码读写SDRAM 不带仿真

; Enable Clock Latency                                           ; Off                ;                 ;                           ;                                       ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;                 ;                           ;                                       ;
; Number of source nodes to report per destination node          ; 10                 ;                 ;                           ;                                       ;
; Number of destination nodes to report                          ; 10                 ;                 ;                           ;                                       ;
; Number of paths to report                                      ; 200                ;                 ;                           ;                                       ;
; Report Minimum Timing Checks                                   ; Off                ;                 ;                           ;                                       ;
; Use Fast Timing Models                                         ; Off                ;                 ;                           ;                                       ;
; Report IO Paths Separately                                     ; Off                ;                 ;                           ;                                       ;
; Perform Multicorner Analysis                                   ; On                 ;                 ;                           ;                                       ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;                 ;                           ;                                       ;
; Cut Timing Path                                                ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe7|dffe8a   ; dcfifo_min1                           ;
; Cut Timing Path                                                ; On                 ; rdptr_g         ; ws_dgrp|dffpipe10|dffe11a ; dcfifo_min1                           ;
; Maximum Delay                                                  ; 100 ns             ;                 ; data_in_d1                ; vga_sys_reset_clk_domain_synch_module ;
+----------------------------------------------------------------+--------------------+-----------------+---------------------------+---------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                             ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                            ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; altpll0:inst|altpll:altpll_component|_clk0 ;                    ; PLL output ; 75.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLK      ; 3                     ; 2                   ; -2.810 ns ;              ;
; altpll0:inst|altpll:altpll_component|_clk1 ;                    ; PLL output ; 75.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLK      ; 3                     ; 2                   ; -3.809 ns ;              ;
; altpll0:inst|altpll:altpll_component|_clk2 ;                    ; PLL output ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLK      ; 1                     ; 2                   ; -2.810 ns ;              ;
; CLK                                        ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP               ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'altpll0:inst|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                ; To                                                                                                                       ; From Clock                                 ; To Clock                                   ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 0.125 ns                                ; 75.71 MHz ( period = 13.208 ns )                    ; vga_sys:inst1|cpu:the_cpu|i_read                                                                                                                    ; vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21]       ; altpll0:inst|altpll:altpll_component|_clk0 ; altpll0:inst|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.733 ns                 ; 12.608 ns               ;
; 0.148 ns                                ; 75.84 MHz ( period = 13.185 ns )                    ; vga_sys:inst1|cpu:the_cpu|ic_fill_tag[13]                                                                                                           ; vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21]       ; altpll0:inst|altpll:altpll_component|_clk0 ; altpll0:inst|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.738 ns                 ; 12.590 ns               ;
; 0.186 ns                                ; 76.06 MHz ( period = 13.147 ns )                    ; vga_sys:inst1|cpu:the_cpu|ic_fill_tag[15]                                                                                                           ; vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21]       ; altpll0:inst|altpll:altpll_component|_clk0 ; altpll0:inst|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.733 ns                 ; 12.547 ns               ;
; 0.245 ns                                ; 76.41 MHz ( period = 13.088 ns )                    ; vga_sys:inst1|cpu:the_cpu|ic_fill_tag[8]                                                                                                            ; vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21]       ; altpll0:inst|altpll:altpll_component|_clk0 ; altpll0:inst|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.714 ns                 ; 12.469 ns               ;
; 0.249 ns                                ; 76.43 MHz ( period = 13.084 ns )                    ; vga_sys:inst1|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_dbs_address[1]                                                         ; vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21]       ; altpll0:inst|altpll:altpll_component|_clk0 ; altpll0:inst|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.738 ns                 ; 12.489 ns               ;