vga_system.tan.rpt

来自「verilog代码读写SDRAM 不带仿真」· RPT 代码 · 共 191 行 · 第 1/5 页

programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-----------------------------------------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+
; Type                                                      ; Slack    ; Required Time                    ; Actual Time                      ; From                                                                                                                                                                                                            ; To                                                                                                                                                                                                              ; From Clock                                 ; To Clock                                   ; Failed Paths ;
+-----------------------------------------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+
; Worst-case tsu                                            ; N/A      ; None                             ; 6.847 ns                         ; altera_internal_jtag~RUNIDLEUSER                                                                                                                                                                                ; vga_sys:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|monitor_go                                                                                                ; --                                         ; CLK                                        ; 0            ;
; Worst-case tco                                            ; N/A      ; None                             ; 9.296 ns                         ; vga_sys:inst1|led_pio:the_led_pio|data_out[1]                                                                                                                                                                   ; LED[1]                                                                                                                                                                                                          ; CLK                                        ; --                                         ; 0            ;
; Worst-case tpd                                            ; N/A      ; None                             ; 3.026 ns                         ; altera_internal_jtag~TDO                                                                                                                                                                                        ; altera_reserved_tdo                                                                                                                                                                                             ; --                                         ; --                                         ; 0            ;
; Worst-case th                                             ; N/A      ; None                             ; 1.932 ns                         ; altera_internal_jtag~TDIUTAP                                                                                                                                                                                    ; sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]                                                                                                                                                      ; --                                         ; altera_internal_jtag~TCKUTAP               ; 0            ;
; Clock Setup: 'altpll0:inst|altpll:altpll_component|_clk0' ; 0.125 ns ; 75.00 MHz ( period = 13.333 ns ) ; 75.71 MHz ( period = 13.208 ns ) ; vga_sys:inst1|cpu:the_cpu|i_read                                                                                                                                                                                ; vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21]                                                                                              ; altpll0:inst|altpll:altpll_component|_clk0 ; altpll0:inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altpll0:inst|altpll:altpll_component|_clk2' ; 8.799 ns ; 25.00 MHz ( period = 40.000 ns ) ; N/A                              ; vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out                                                                                                                     ; vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22]                                                                                                                   ; altpll0:inst|altpll:altpll_component|_clk0 ; altpll0:inst|altpll:altpll_component|_clk2 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'               ; N/A      ; None                             ; 92.18 MHz ( period = 10.848 ns ) ; vga_sys:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[0]                                ; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                                                                                                ; altera_internal_jtag~TCKUTAP               ; altera_internal_jtag~TCKUTAP               ; 0            ;
; Clock Hold: 'altpll0:inst|altpll:altpll_component|_clk0'  ; 0.499 ns ; 75.00 MHz ( period = 13.333 ns ) ; N/A                              ; vga_sys:inst1|sdram:the_sdram|i_cmd[4]                                                                                                                                                                          ; vga_sys:inst1|sdram:the_sdram|i_cmd[4]                                                                                                                                                                          ; altpll0:inst|altpll:altpll_component|_clk0 ; altpll0:inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'altpll0:inst|altpll:altpll_component|_clk2'  ; 0.739 ns ; 25.00 MHz ( period = 40.000 ns ) ; N/A                              ; vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|vga_fifo:line_fifo|dcfifo:dcfifo_component|dcfifo_min1:auto_generated|alt_synch_pipe_0e8:rs_dgwp|dffpipe_qe9:dffpipe7|dffe8a[7] ; vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|vga_fifo:line_fifo|dcfifo:dcfifo_component|dcfifo_min1:auto_generated|alt_synch_pipe_0e8:rs_dgwp|dffpipe_qe9:dffpipe7|dffe9a[7] ; altpll0:inst|altpll:altpll_component|_clk2 ; altpll0:inst|altpll:altpll_component|_clk2 ; 0            ;
; Total number of failed paths                              ;          ;                                  ;                                  ;                                                                                                                                                                                                                 ;                                                                                                                                                                                                                 ;                                            ;                                            ; 0            ;
+-----------------------------------------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                                                  ;
+----------------------------------------------------------------+--------------------+-----------------+---------------------------+---------------------------------------+
; Option                                                         ; Setting            ; From            ; To                        ; Entity Name                           ;
+----------------------------------------------------------------+--------------------+-----------------+---------------------------+---------------------------------------+
; Device Name                                                    ; EP2C35F484C8       ;                 ;                           ;                                       ;
; Timing Models                                                  ; Final              ;                 ;                           ;                                       ;
; Default hold multicycle                                        ; Same as Multicycle ;                 ;                           ;                                       ;
; Cut paths between unrelated clock domains                      ; On                 ;                 ;                           ;                                       ;
; Cut off read during write signal paths                         ; On                 ;                 ;                           ;                                       ;
; Cut off feedback from I/O pins                                 ; On                 ;                 ;                           ;                                       ;
; Report Combined Fast/Slow Timing                               ; Off                ;                 ;                           ;                                       ;
; Ignore Clock Settings                                          ; Off                ;                 ;                           ;                                       ;
; Analyze latches as synchronous elements                        ; On                 ;                 ;                           ;                                       ;
; Enable Recovery/Removal analysis                               ; Off                ;                 ;                           ;                                       ;