dpram_5h21.tdf

verilog代码读写SDRAM 不带仿真

--altdpram DEVICE_FAMILY="Cyclone II" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=8 WIDTHAD=6 data inclock outclock outclocken q rdaddress wraddress wren CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 7.2SP2 cbx_altdpram 2007:04:25:14:55:30:SJ cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END


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--  without limitation, that your use is for the sole purpose of 
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FUNCTION altsyncram_9tl1 (address_a[5..0], address_b[5..0], clock0, clock1, clocken1, data_a[7..0], wren_a)
RETURNS ( q_b[7..0]);

--synthesis_resources = M4K 1 
SUBDESIGN dpram_5h21
( 
	data[7..0]	:	input;
	inclock	:	input;
	outclock	:	input;
	outclocken	:	input;
	q[7..0]	:	output;
	rdaddress[5..0]	:	input;
	wraddress[5..0]	:	input;
	wren	:	input;
) 
VARIABLE 
	altsyncram2 : altsyncram_9tl1;

BEGIN 
	altsyncram2.address_a[] = wraddress[];
	altsyncram2.address_b[] = rdaddress[];
	altsyncram2.clock0 = inclock;
	altsyncram2.clock1 = outclock;
	altsyncram2.clocken1 = outclocken;
	altsyncram2.data_a[] = data[];
	altsyncram2.wren_a = wren;
	q[] = altsyncram2.q_b[];
END;
--VALID FILE