dffpipe_re9.tdf

verilog代码读写SDRAM 不带仿真

--dffpipe DELAY=2 WIDTH=11 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 7.2SP2 cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END


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--synthesis_resources = reg 22 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_re9
( 
	clock	:	input;
	clrn	:	input;
	d[10..0]	:	input;
	q[10..0]	:	output;
) 
VARIABLE 
	dffe11a[10..0] : dffe;
	dffe12a[10..0] : dffe;
	ena	: NODE;
	prn	: NODE;
	sclr	: NODE;

BEGIN 
	dffe11a[].clk = clock;
	dffe11a[].clrn = clrn;
	dffe11a[].d = (d[] & (! sclr));
	dffe11a[].ena = ena;
	dffe11a[].prn = prn;
	dffe12a[].clk = clock;
	dffe12a[].clrn = clrn;
	dffe12a[].d = (dffe11a[].q & (! sclr));
	dffe12a[].ena = ena;
	dffe12a[].prn = prn;
	ena = VCC;
	prn = VCC;
	q[] = dffe12a[].q;
	sclr = GND;
END;
--VALID FILE