alt_synch_pipe_1e8.tdf

verilog代码读写SDRAM 不带仿真

--dffpipe DELAY=2 WIDTH=11 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF
--VERSION_BEGIN 7.2SP2 cbx_a_gray2bin 2006:02:28:14:37:30:SJ cbx_a_graycounter 2007:02:22:13:58:22:SJ cbx_altdpram 2007:04:25:14:55:30:SJ cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_dcfifo 2007:07:31:10:15:48:SJ cbx_fifo_common 2007:04:09:14:30:26:SJ cbx_flex10ke 2006:01:09:11:13:48:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_counter 2007:08:07:01:40:08:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_scfifo 2007:04:06:15:45:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END


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FUNCTION dffpipe_re9 (clock, clrn, d[10..0])
RETURNS ( q[10..0]);

--synthesis_resources = reg 22 
OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF";

SUBDESIGN alt_synch_pipe_1e8
( 
	clock	:	input;
	clrn	:	input;
	d[10..0]	:	input;
	q[10..0]	:	output;
) 
VARIABLE 
	dffpipe10 : dffpipe_re9;

BEGIN 
	dffpipe10.clock = clock;
	dffpipe10.clrn = clrn;
	dffpipe10.d[] = d[];
	q[] = dffpipe10.q[];
END;
--VALID FILE