mux_1u7.tdf

来自「verilog代码读写SDRAM 不带仿真」· TDF 代码 · 共 42 行

--lpm_mux DEVICE_FAMILY="Cyclone II" LPM_SIZE=2 LPM_WIDTH=1 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 7.2SP2 cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 1 
SUBDESIGN mux_1u7
( 
	data[1..0]	:	input;
	result[0..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[0..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data601w[1..0]	: WIRE;
	w_result602w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( ((sel_node[] & w_data601w[1..1]) # ((! sel_node[]) & w_data601w[0..0])));
	sel_node[] = ( sel[0..0]);
	w_data601w[] = ( data[1..0]);
	w_result602w = ((sel_node[] & w_data601w[1..1]) # ((! sel_node[]) & w_data601w[0..0]));
END;
--VALID FILE