altsyncram_ji01.tdf

verilog代码读写SDRAM 不带仿真

--altsyncram ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone II" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="M4K" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 WIDTHAD_B=10 address_a address_b addressstall_b clock0 clock1 data_a q_b wren_a
--VERSION_BEGIN 7.2SP2 cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END


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--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.


FUNCTION altsyncram_veb1 (address_a[9..0], address_b[9..0], addressstall_a, clock0, clock1, clocken1, data_a[31..0], data_b[31..0], wren_a, wren_b)
RETURNS ( q_a[31..0], q_b[31..0]);

--synthesis_resources = M4K 8 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_ji01
( 
	address_a[9..0]	:	input;
	address_b[9..0]	:	input;
	addressstall_b	:	input;
	clock0	:	input;
	clock1	:	input;
	data_a[31..0]	:	input;
	q_b[31..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	altsyncram3 : altsyncram_veb1;

BEGIN 
	altsyncram3.address_a[] = address_b[];
	altsyncram3.address_b[] = address_a[];
	altsyncram3.addressstall_a = addressstall_b;
	altsyncram3.clock0 = clock1;
	altsyncram3.clock1 = clock0;
	altsyncram3.clocken1 = wren_a;
	altsyncram3.data_a[] = B"11111111111111111111111111111111";
	altsyncram3.data_b[] = data_a[];
	altsyncram3.wren_a = B"0";
	altsyncram3.wren_b = wren_a;
	q_b[] = altsyncram3.q_a[];
END;
--VALID FILE