vga_system.fit.qmsg

verilog代码读写SDRAM 不带仿真

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "vga_sys:inst1\|freedev_vga_inst:the_freedev_vga_inst\|freedev_vga:the_freedev_vga\|vga_fifo:line_fifo\|dcfifo:dcfifo_component\|dcfifo_min1:auto_generated\|dffpipe_mcc:rdaclr\|dffe5a\[0\]  " "Info: Automatically promoted node vga_sys:inst1\|freedev_vga_inst:the_freedev_vga_inst\|freedev_vga:the_freedev_vga\|vga_fifo:line_fifo\|dcfifo:dcfifo_component\|dcfifo_min1:auto_generated\|dffpipe_mcc:rdaclr\|dffe5a\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "db/dffpipe_mcc.tdf" "" { Text "D:/FreeDevDAV/example/vga_system/db/dffpipe_mcc.tdf" 32 8 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|vga_fifo:line_fifo|dcfifo:dcfifo_component|dcfifo_min1:auto_generated|dffpipe_mcc:rdaclr|dffe5a[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|vga_fifo:line_fifo|dcfifo:dcfifo_component|dcfifo_min1:auto_generated|dffpipe_mcc:rdaclr|dffe5a[0] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "vga_sys:inst1\|reset_n_sources~1  " "Info: Automatically promoted node vga_sys:inst1\|reset_n_sources~1 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7562 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { vga_sys:inst1|reset_n_sources~1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { vga_sys:inst1|reset_n_sources~1 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Info: Ignoring invalid fast I/O register assignments" {  } {  } 0 0 "Ignoring invalid fast I/O register assignments" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}