prev_cmp_vga_system.map.qmsg

verilog代码读写SDRAM 不带仿真

{ "Info" "ISGN_ELABORATION_HEADER" "vga_sys:inst1\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"vga_sys:inst1\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 513 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_m6e1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_m6e1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_m6e1 " "Info: Found entity 1: altsyncram_m6e1" {  } { { "db/altsyncram_m6e1.tdf" "" { Text "D:/FreeDevDAV/example/vga_system/db/altsyncram_m6e1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_m6e1 vga_sys:inst1\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_m6e1:auto_generated " "Info: Elaborating entity \"altsyncram_m6e1\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_m6e1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_dc_tag_module vga_sys:inst1\|cpu:the_cpu\|cpu_dc_tag_module:cpu_dc_tag " "Info: Elaborating entity \"cpu_dc_tag_module\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_dc_tag_module:cpu_dc_tag\"" {  } { { "cpu.v" "cpu_dc_tag" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 8741 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram vga_sys:inst1\|cpu:the_cpu\|cpu_dc_tag_module:cpu_dc_tag\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_dc_tag_module:cpu_dc_tag\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "the_altsyncram" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 617 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "vga_sys:inst1\|cpu:the_cpu\|cpu_dc_tag_module:cpu_dc_tag\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"vga_sys:inst1\|cpu:the_cpu\|cpu_dc_tag_module:cpu_dc_tag\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 617 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_lde1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_lde1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_lde1 " "Info: Found entity 1: altsyncram_lde1" {  } { { "db/altsyncram_lde1.tdf" "" { Text "D:/FreeDevDAV/example/vga_system/db/altsyncram_lde1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_lde1 vga_sys:inst1\|cpu:the_cpu\|cpu_dc_tag_module:cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_lde1:auto_generated " "Info: Elaborating entity \"altsyncram_lde1\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_dc_tag_module:cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_lde1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_dc_data_module vga_sys:inst1\|cpu:the_cpu\|cpu_dc_data_module:cpu_dc_data " "Info: Elaborating entity \"cpu_dc_data_module\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_dc_data_module:cpu_dc_data\"" {  } { { "cpu.v" "cpu_dc_data" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 8797 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram vga_sys:inst1\|cpu:the_cpu\|cpu_dc_data_module:cpu_dc_data\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_dc_data_module:cpu_dc_data\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "the_altsyncram" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 725 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "vga_sys:inst1\|cpu:the_cpu\|cpu_dc_data_module:cpu_dc_data\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"vga_sys:inst1\|cpu:the_cpu\|cpu_dc_data_module:cpu_dc_data\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 725 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_uce1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_uce1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_uce1 " "Info: Found entity 1: altsyncram_uce1" {  } { { "db/altsyncram_uce1.tdf" "" { Text "D:/FreeDevDAV/example/vga_system/db/altsyncram_uce1.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_uce1 vga_sys:inst1\|cpu:the_cpu\|cpu_dc_data_module:cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_uce1:auto_generated " "Info: Elaborating entity \"altsyncram_uce1\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_dc_data_module:cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_uce1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_chp1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_chp1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_chp1 " "Info: Found entity 1: altsyncram_chp1" {  } { { "db/altsyncram_chp1.tdf" "" { Text "D:/FreeDevDAV/example/vga_system/db/altsyncram_chp1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_chp1 vga_sys:inst1\|cpu:the_cpu\|cpu_dc_data_module:cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_uce1:auto_generated\|altsyncram_chp1:altsyncram1 " "Info: Elaborating entity \"altsyncram_chp1\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_dc_data_module:cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_uce1:auto_generated\|altsyncram_chp1:altsyncram1\"" {  } { { "db/altsyncram_uce1.tdf" "altsyncram1" { Text "D:/FreeDevDAV/example/vga_system/db/altsyncram_uce1.tdf" 39 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_dc_victim_module vga_sys:inst1\|cpu:the_cpu\|cpu_dc_victim_module:cpu_dc_victim " "Info: Elaborating entity \"cpu_dc_victim_module\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_dc_victim_module:cpu_dc_victim\"" {  } { { "cpu.v" "cpu_dc_victim" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 8814 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram vga_sys:inst1\|cpu:the_cpu\|cpu_dc_victim_module:cpu_dc_victim\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_dc_victim_module:cpu_dc_victim\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "the_altsyncram" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 828 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "vga_sys:inst1\|cpu:the_cpu\|cpu_dc_victim_module:cpu_dc_victim\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"vga_sys:inst1\|cpu:the_cpu\|cpu_dc_victim_module:cpu_dc_victim\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 828 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_reb1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_reb1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_reb1 " "Info: Found entity 1: altsyncram_reb1" {  } { { "db/altsyncram_reb1.tdf" "" { Text "D:/FreeDevDAV/example/vga_system/db/altsyncram_reb1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_reb1 vga_sys:inst1\|cpu:the_cpu\|cpu_dc_victim_module:cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_reb1:auto_generated " "Info: Elaborating entity \"altsyncram_reb1\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_dc_victim_module:cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_reb1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_mult_cell.v 1 1 " "Warning: Using design file cpu_mult_cell.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_mult_cell " "Info: Found entity 1: cpu_mult_cell" {  } { { "cpu_mult_cell.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu_mult_cell.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_mult_cell vga_sys:inst1\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell " "Info: Elaborating entity \"cpu_mult_cell\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\"" {  } { { "cpu.v" "the_cpu_mult_cell" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 9637 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}