prev_cmp_vga_system.map.qmsg

verilog代码读写SDRAM 不带仿真

{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "auto_dissolve vga_sys.v(6032) " "Warning (10335): Unrecognized synthesis attribute \"auto_dissolve\" at vga_sys.v(6032)" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6032 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "auto_dissolve vga_sys.v(6313) " "Warning (10335): Unrecognized synthesis attribute \"auto_dissolve\" at vga_sys.v(6313)" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6313 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "vga_sys.v 24 24 " "Warning: Using design file vga_sys.v, which is not specified as a design file for the current project, but contains definitions for 24 design units and 24 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 burstcount_fifo_for_burst_0_upstream_module " "Info: Found entity 1: burstcount_fifo_for_burst_0_upstream_module" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 rdv_fifo_for_freedev_vga_inst_avalon_master_to_burst_0_upstream_module " "Info: Found entity 2: rdv_fifo_for_freedev_vga_inst_avalon_master_to_burst_0_upstream_module" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 450 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 burst_0_upstream_arbitrator " "Info: Found entity 3: burst_0_upstream_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 874 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "4 burst_0_downstream_arbitrator " "Info: Found entity 4: burst_0_downstream_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 1312 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "5 cpu_jtag_debug_module_arbitrator " "Info: Found entity 5: cpu_jtag_debug_module_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 1572 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "6 cpu_data_master_arbitrator " "Info: Found entity 6: cpu_data_master_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 2020 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "7 cpu_instruction_master_arbitrator " "Info: Found entity 7: cpu_instruction_master_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 2547 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "8 freedev_vga_inst_avalon_slave_0_arbitrator " "Info: Found entity 8: freedev_vga_inst_avalon_slave_0_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 2872 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "9 freedev_vga_inst_avalon_master_arbitrator " "Info: Found entity 9: freedev_vga_inst_avalon_master_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 3159 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "10 jtag_uart_avalon_jtag_slave_arbitrator " "Info: Found entity 10: jtag_uart_avalon_jtag_slave_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 3465 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "11 led_pio_s1_arbitrator " "Info: Found entity 11: led_pio_s1_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 3776 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "12 rdv_fifo_for_burst_0_downstream_to_sdram_s1_module " "Info: Found entity 12: rdv_fifo_for_burst_0_downstream_to_sdram_s1_module" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 4039 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "13 rdv_fifo_for_cpu_data_master_to_sdram_s1_module " "Info: Found entity 13: rdv_fifo_for_cpu_data_master_to_sdram_s1_module" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 4387 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "14 rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module " "Info: Found entity 14: rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 4735 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "15 sdram_s1_arbitrator " "Info: Found entity 15: sdram_s1_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 5083 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "16 sys_clk_timer_s1_arbitrator " "Info: Found entity 16: sys_clk_timer_s1_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 5731 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "17 sysid_control_slave_arbitrator " "Info: Found entity 17: sysid_control_slave_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6012 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "18 tristate_bridge_avalon_slave_arbitrator " "Info: Found entity 18: tristate_bridge_avalon_slave_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6261 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "19 tristate_bridge_bridge_arbitrator " "Info: Found entity 19: tristate_bridge_bridge_arbitrator" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7232 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "20 vga_sys_reset_clk_domain_synch_module " "Info: Found entity 20: vga_sys_reset_clk_domain_synch_module" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7245 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "21 vga_sys " "Info: Found entity 21: vga_sys" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7290 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "22 cfi_flash_lane0_module " "Info: Found entity 22: cfi_flash_lane0_module" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 8271 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "23 cfi_flash_lane1_module " "Info: Found entity 23: cfi_flash_lane1_module" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 8362 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "24 cfi_flash " "Info: Found entity 24: cfi_flash" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 8453 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_sys vga_sys:inst1 " "Info: Elaborating entity \"vga_sys\" for hierarchy \"vga_sys:inst1\"" {  } { { "vga_system.bdf" "inst1" { Schematic "D:/FreeDevDAV/example/vga_system/vga_system.bdf" { { 336 168 560 912 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "burst_0_upstream_arbitrator vga_sys:inst1\|burst_0_upstream_arbitrator:the_burst_0_upstream " "Info: Elaborating entity \"burst_0_upstream_arbitrator\" for hierarchy \"vga_sys:inst1\|burst_0_upstream_arbitrator:the_burst_0_upstream\"" {  } { { "vga_sys.v" "the_burst_0_upstream" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7636 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "burstcount_fifo_for_burst_0_upstream_module vga_sys:inst1\|burst_0_upstream_arbitrator:the_burst_0_upstream\|burstcount_fifo_for_burst_0_upstream_module:burstcount_fifo_for_burst_0_upstream " "Info: Elaborating entity \"burstcount_fifo_for_burst_0_upstream_module\" for hierarchy \"vga_sys:inst1\|burst_0_upstream_arbitrator:the_burst_0_upstream\|burstcount_fifo_for_burst_0_upstream_module:burstcount_fifo_for_burst_0_upstream\"" {  } { { "vga_sys.v" "burstcount_fifo_for_burst_0_upstream" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 1108 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rdv_fifo_for_freedev_vga_inst_avalon_master_to_burst_0_upstream_module vga_sys:inst1\|burst_0_upstream_arbitrator:the_burst_0_upstream\|rdv_fifo_for_freedev_vga_inst_avalon_master_to_burst_0_upstream_module:rdv_fifo_for_freedev_vga_inst_avalon_master_to_burst_0_upstream " "Info: Elaborating entity \"rdv_fifo_for_freedev_vga_inst_avalon_master_to_burst_0_upstream_module\" for hierarchy \"vga_sys:inst1\|burst_0_upstream_arbitrator:the_burst_0_upstream\|rdv_fifo_for_freedev_vga_inst_avalon_master_to_burst_0_upstream_module:rdv_fifo_for_freedev_vga_inst_avalon_master_to_burst_0_upstream\"" {  } { { "vga_sys.v" "rdv_fifo_for_freedev_vga_inst_avalon_master_to_burst_0_upstream" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 1161 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "burst_0_downstream_arbitrator vga_sys:inst1\|burst_0_downstream_arbitrator:the_burst_0_downstream " "Info: Elaborating entity \"burst_0_downstream_arbitrator\" for hierarchy \"vga_sys:inst1\|burst_0_downstream_arbitrator:the_burst_0_downstream\"" {  } { { "vga_sys.v" "the_burst_0_downstream" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7661 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "burst_0.v 1 1 " "Warning: Using design file burst_0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 burst_0 " "Info: Found entity 1: burst_0" {  } { { "burst_0.v" "" { Text "D:/FreeDevDAV/example/vga_system/burst_0.v" 52 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "burst_0 vga_sys:inst1\|burst_0:the_burst_0 " "Info: Elaborating entity \"burst_0\" for hierarchy \"vga_sys:inst1\|burst_0:the_burst_0\"" {  } { { "vga_sys.v" "the_burst_0" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7690 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_jtag_debug_module_arbitrator vga_sys:inst1\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module " "Info: Elaborating entity \"cpu_jtag_debug_module_arbitrator\" for hierarchy \"vga_sys:inst1\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\"" {  } { { "vga_sys.v" "the_cpu_jtag_debug_module" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7730 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_data_master_arbitrator vga_sys:inst1\|cpu_data_master_arbitrator:the_cpu_data_master " "Info: Elaborating entity \"cpu_data_master_arbitrator\" for hierarchy \"vga_sys:inst1\|cpu_data_master_arbitrator:the_cpu_data_master\"" {  } { { "vga_sys.v" "the_cpu_data_master" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7812 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_instruction_master_arbitrator vga_sys:inst1\|cpu_instruction_master_arbitrator:the_cpu_instruction_master " "Info: Elaborating entity \"cpu_instruction_master_arbitrator\" for hierarchy \"vga_sys:inst1\|cpu_instruction_master_arbitrator:the_cpu_instruction_master\"" {  } { { "vga_sys.v" "the_cpu_instruction_master" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7852 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "cpu.v 30 30 " "Warning: Using design file cpu.v, which is not specified as a design file for the current project, but contains definitions for 30 design units and 30 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_ic_data_module " "Info: Found entity 1: cpu_ic_data_module" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 cpu_ic_tag_module " "Info: Found entity 2: cpu_ic_tag_module" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 123 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 cpu_bht_module " "Info: Found entity 3: cpu_bht_module" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 227 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "4 cpu_register_bank_a_module " "Info: Found entity 4: cpu_register_bank_a_module" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 331 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "5 cpu_register_bank_b_module " "Info: Found entity 5: cpu_register_bank_b_module" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 435 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "6 cpu_dc_tag_module " "Info: Found entity 6: cpu_dc_tag_module" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 539 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "7 cpu_dc_data_module " "Info: Found entity 7: cpu_dc_data_module" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 643 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "8 cpu_dc_victim_module " "Info: Found entity 8: cpu_dc_victim_module" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 751 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "9 cpu_nios2_oci_debug " "Info: Found entity 9: cpu_nios2_oci_debug" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 853 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "10 cpu_ociram_lpm_dram_bdp_component_module " "Info: Found entity 10: cpu_ociram_lpm_dram_bdp_component_module" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 970 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "11 cpu_nios2_ocimem " "Info: Found entity 11: cpu_nios2_ocimem" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 1060 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "12 cpu_nios2_avalon_reg " "Info: Found entity 12: cpu_nios2_avalon_reg" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 1203 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "13 cpu_nios2_oci_break " "Info: Found entity 13: cpu_nios2_oci_break" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 1294 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "14 cpu_nios2_oci_xbrk " "Info: Found entity 14: cpu_nios2_oci_xbrk" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 1769 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "15 cpu_nios2_oci_match_paired " "Info: Found entity 15: cpu_nios2_oci_match_paired" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 2058 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "16 cpu_nios2_oci_match_single " "Info: Found entity 16: cpu_nios2_oci_match_single" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 2093 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "17 cpu_nios2_oci_dbrk " "Info: Found entity 17: cpu_nios2_oci_dbrk" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 2126 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "18 cpu_nios2_oci_itrace " "Info: Found entity 18: cpu_nios2_oci_itrace" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 2354 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "19 cpu_nios2_oci_td_mode " "Info: Found entity 19: cpu_nios2_oci_td_mode" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 2637 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "20 cpu_nios2_oci_dtrace " "Info: Found entity 20: cpu_nios2_oci_dtrace" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 2701 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "21 cpu_nios2_oci_compute_tm_count " "Info: Found entity 21: cpu_nios2_oci_compute_tm_count" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 2791 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "22 cpu_nios2_oci_fifowp_inc " "Info: Found entity 22: cpu_nios2_oci_fifowp_inc" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 2859 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "23 cpu_nios2_oci_fifocount_inc " "Info: Found entity 23: cpu_nios2_oci_fifocount_inc" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 2898 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "24 cpu_nios2_oci_fifo " "Info: Found entity 24: cpu_nios2_oci_fifo" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 2941 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "25 cpu_nios2_oci_pib " "Info: Found entity 25: cpu_nios2_oci_pib" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 3426 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "26 cpu_traceram_lpm_dram_bdp_component_module " "Info: Found entity 26: cpu_traceram_lpm_dram_bdp_component_module" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 3491 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "27 cpu_nios2_oci_im " "Info: Found entity 27: cpu_nios2_oci_im" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 3577 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "28 cpu_nios2_performance_monitors " "Info: Found entity 28: cpu_nios2_performance_monitors" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 3711 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "29 cpu_nios2_oci " "Info: Found entity 29: cpu_nios2_oci" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 3724 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "30 cpu " "Info: Found entity 30: cpu" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 4247 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu vga_sys:inst1\|cpu:the_cpu " "Info: Elaborating entity \"cpu\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\"" {  } { { "vga_sys.v" "the_cpu" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7884 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_test_bench.v 1 1 " "Warning: Using design file cpu_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_test_bench " "Info: Found entity 1: cpu_test_bench" {  } { { "cpu_test_bench.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu_test_bench.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_test_bench vga_sys:inst1\|cpu:the_cpu\|cpu_test_bench:the_cpu_test_bench " "Info: Elaborating entity \"cpu_test_bench\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_test_bench:the_cpu_test_bench\"" {  } { { "cpu.v" "the_cpu_test_bench" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 6143 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_ic_data_module vga_sys:inst1\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data " "Info: Elaborating entity \"cpu_ic_data_module\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\"" {  } { { "cpu.v" "cpu_ic_data" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 7143 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram vga_sys:inst1\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"vga_sys:inst1\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "the_altsyncram" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 98 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "vga_sys:inst1\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"vga_sys:inst1\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram\"" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 98 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_cub1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_cub1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_cub1 " "Info: Found entity 1: altsyncram_cub1" {  } { { "db/altsyncram_cub1.tdf" "" { Text "D:/FreeDevDAV/example/vga_system/db/altsyncram_cub1.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}