vga_system.tan.qmsg

来自「verilog代码读写SDRAM 不带仿真」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Info" "ITAN_NO_REG2REG_EXIST" "CLK " "Info: No valid register-to-register data paths exist for clock \"CLK\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register vga_sys:inst1\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|sr\[0\] register sld_hub:sld_hub_inst\|hub_tdo_reg 92.18 MHz 10.848 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 92.18 MHz between source register \"vga_sys:inst1\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|sr\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 10.848 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.134 ns + Longest register register " "Info: + Longest register to register delay is 5.134 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_sys:inst1\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|sr\[0\] 1 REG LCFF_X24_Y22_N23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y22_N23; Fanout = 2; REG Node = 'vga_sys:inst1\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|sr\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { vga_sys:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[0] } "NODE_NAME" } } { "cpu_jtag_debug_module.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu_jtag_debug_module.v" 230 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.419 ns) + CELL(0.650 ns) 3.069 ns sld_hub:sld_hub_inst\|hub_tdo_reg~324 2 COMB LCCOMB_X20_Y11_N22 1 " "Info: 2: + IC(2.419 ns) + CELL(0.650 ns) = 3.069 ns; Loc. = LCCOMB_X20_Y11_N22; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~324'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.069 ns" { vga_sys:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[0] sld_hub:sld_hub_inst|hub_tdo_reg~324 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.358 ns) + CELL(0.623 ns) 4.050 ns sld_hub:sld_hub_inst\|hub_tdo_reg~325 3 COMB LCCOMB_X20_Y11_N28 1 " "Info: 3: + IC(0.358 ns) + CELL(0.623 ns) = 4.050 ns; Loc. = LCCOMB_X20_Y11_N28; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~325'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.981 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~324 sld_hub:sld_hub_inst|hub_tdo_reg~325 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(0.616 ns) 5.026 ns sld_hub:sld_hub_inst\|hub_tdo_reg~326 4 COMB LCCOMB_X20_Y11_N10 1 " "Info: 4: + IC(0.360 ns) + CELL(0.616 ns) = 5.026 ns; Loc. = LCCOMB_X20_Y11_N10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~326'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.976 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~325 sld_hub:sld_hub_inst|hub_tdo_reg~326 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.134 ns sld_hub:sld_hub_inst\|hub_tdo_reg 5 REG LCFF_X20_Y11_N11 2 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 5.134 ns; Loc. = LCFF_X20_Y11_N11; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~326 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.997 ns ( 38.90 % ) " "Info: Total cell delay = 1.997 ns ( 38.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.137 ns ( 61.10 % ) " "Info: Total interconnect delay = 3.137 ns ( 61.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.134 ns" { vga_sys:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[0] sld_hub:sld_hub_inst|hub_tdo_reg~324 sld_hub:sld_hub_inst|hub_tdo_reg~325 sld_hub:sld_hub_inst|hub_tdo_reg~326 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.134 ns" { vga_sys:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[0] {} sld_hub:sld_hub_inst|hub_tdo_reg~324 {} sld_hub:sld_hub_inst|hub_tdo_reg~325 {} sld_hub:sld_hub_inst|hub_tdo_reg~326 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 2.419ns 0.358ns 0.360ns 0.000ns } { 0.000ns 0.650ns 0.623ns 0.616ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.026 ns - Smallest " "Info: - Smallest clock skew is -0.026 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.662 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.662 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/72/quartus/bin/TimingClosur