vga_system.tan.qmsg

来自「verilog代码读写SDRAM 不带仿真」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 register vga_sys:inst1\|cpu:the_cpu\|i_read register vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|tristate_bridge_address\[21\] 125 ps " "Info: Slack time is 125 ps for clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" between source register \"vga_sys:inst1\|cpu:the_cpu\|i_read\" and destination register \"vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|tristate_bridge_address\[21\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "75.71 MHz 13.208 ns " "Info: Fmax is 75.71 MHz (period= 13.208 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "12.733 ns + Largest register register " "Info: + Largest register to register requirement is 12.733 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "13.333 ns + " "Info: + Setup relationship between source and destination is 13.333 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.523 ns " "Info: + Latch edge is 10.523 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst\|altpll:altpll_component\|_clk0 13.333 ns -2.810 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" is 13.333 ns with  offset of -2.810 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.810 ns " "Info: - Launch edge is -2.810 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst\|altpll:altpll_component\|_clk0 13.333 ns -2.810 ns  50 " "Info: Clock period of Source clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" is 13.333 ns with  offset of -2.810 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.195 ns + Largest " "Info: + Largest clock skew is -0.195 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 destination 3.017 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" to destination register is 3.017 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll0:inst\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.373 ns) + CELL(0.000 ns) 1.373 ns altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G7 3896 " "Info: 2: + IC(1.373 ns) + CELL(0.000 ns) = 1.373 ns; Loc. = CLKCTRL_G7; Fanout = 3896; COMB Node = 'altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.373 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.310 ns) + CELL(0.334 ns) 3.017 ns vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|tristate_bridge_address\[21\] 3 REG IOC_X0_Y2_N1 1 " "Info: 3: + IC(1.310 ns) + CELL(0.334 ns) = 3.017 ns; Loc. = IOC_X0_Y2_N1; Fanout = 1; REG Node = 'vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|tristate_bridge_address\[21\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.644 ns" { altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6930 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.334 ns ( 11.07 % ) " "Info: Total cell delay = 0.334 ns ( 11.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.683 ns ( 88.93 % ) " "Info: Total interconnect delay = 2.683 ns ( 88.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.017 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.017 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} altpll0:inst|altpll:altpll_component|_clk0~clkctrl {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] {} } { 0.000ns 1.373ns 1.310ns } { 0.000ns 0.000ns 0.334ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 source 3.212 ns - Longest register " "Info: - Longest clock path from clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" to source register is 3.212 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll0:inst\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.373 ns) + CELL(0.000 ns) 1.373 ns altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G7 3896 " "Info: 2: + IC(1.373 ns) + CELL(0.000 ns) = 1.373 ns; Loc. = CLKCTRL_G7; Fanout = 3896; COMB Node = 'altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.373 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.173 ns) + CELL(0.666 ns) 3.212 ns vga_sys:inst1\|cpu:the_cpu\|i_read 3 REG LCFF_X37_Y20_N29 29 " "Info: 3: + IC(1.173 ns) + CELL(0.666 ns) = 3.212 ns; Loc. = LCFF_X37_Y20_N29; Fanout = 29; REG Node = 'vga_sys:inst1\|cpu:the_cpu\|i_read'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.839 ns" { altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|cpu:the_cpu|i_read } "NODE_NAME" } } { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 4288 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 20.73 % ) " "Info: Total cell delay = 0.666 ns ( 20.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.546 ns ( 79.27 % ) " "Info: Total interconnect delay = 2.546 ns ( 79.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.212 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|cpu:the_cpu|i_read } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.212 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} altpll0:inst|altpll:altpll_component|_clk0~clkctrl {} vga_sys:inst1|cpu:the_cpu|i_read {} } { 0.000ns 1.373ns 1.173ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.017 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.017 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} altpll0:inst|altpll:altpll_component|_clk0~clkctrl {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] {} } { 0.000ns 1.373ns 1.310ns } { 0.000ns 0.000ns 0.334ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.212 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|cpu:the_cpu|i_read } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.212 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} altpll0:inst|altpll:altpll_component|_clk0~clkctrl {} vga_sys:inst1|cpu:the_cpu|i_read {} } { 0.000ns 1.373ns 1.173ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 4288 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.101 ns - " "Info: - Micro setup delay of destination is 0.101 ns" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6930 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.017 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.017 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} altpll0:inst|altpll:altpll_component|_clk0~clkctrl {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] {} } { 0.000ns 1.373ns 1.310ns } { 0.000ns 0.000ns 0.334ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.212 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|cpu:the_cpu|i_read } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.212 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} altpll0:inst|altpll:altpll_component|_clk0~clkctrl {} vga_sys:inst1|cpu:the_cpu|i_read {} } { 0.000ns 1.373ns 1.173ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.608 ns - Longest register register " "Info: - Longest register to register delay is 12.608 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_sys:inst1\|cpu:the_cpu\|i_read 1 REG LCFF_X37_Y20_N29 29 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X37_Y20_N29; Fanout = 29; REG Node = 'vga_sys:inst1\|cpu:the_cpu\|i_read'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { vga_sys:inst1|cpu:the_cpu|i_read } "NODE_NAME" } } { "cpu.v" "" { Text "D:/FreeDevDAV/example/vga_system/cpu.v" 4288 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(0.623 ns) 1.738 ns vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|cpu_instruction_master_arbiterlock~29 2 COMB LCCOMB_X34_Y20_N6 2 " "Info: 2: + IC(1.115 ns) + CELL(0.623 ns) = 1.738 ns; Loc. = LCCOMB_X34_Y20_N6; Fanout = 2; COMB Node = 'vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|cpu_instruction_master_arbiterlock~29'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.738 ns" { vga_sys:inst1|cpu:the_cpu|i_read vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_instruction_master_arbiterlock~29 } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6395 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.374 ns) + CELL(0.206 ns) 2.318 ns vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|cpu_data_master_qualified_request_cfi_flash_s1~101 3 COMB LCCOMB_X34_Y20_N24 1 " "Info: 3: + IC(0.374 ns) + CELL(0.206 ns) = 2.318 ns; Loc. = LCCOMB_X34_Y20_N24; Fanout = 1; COMB Node = 'vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|cpu_data_master_qualified_request_cfi_flash_s1~101'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.580 ns" { vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_instruction_master_arbiterlock~29 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1~101 } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6321 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.370 ns) 3.058 ns vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|cpu_data_master_qualified_request_cfi_flash_s1~102 4 COMB LCCOMB_X34_Y20_N20 7 " "Info: 4: + IC(0.370 ns) + CELL(0.370 ns) = 3.058 ns; Loc. = LCCOMB_X34_Y20_N20; Fanout = 7; COMB Node = 'vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|cpu_data_master_qualified_request_cfi_flash_s1~102'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.740 ns" { vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1~101 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1~102 } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6321 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.125 ns) + CELL(0.206 ns) 4.389 ns vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|cpu_data_master_qualified_request_cfi_flash_s1 5 COMB LCCOMB_X33_Y17_N30 9 " "Info: 5: + IC(1.125 ns) + CELL(0.206 ns) = 4.389 ns; Loc. = LCCOMB_X33_Y17_N30; Fanout = 9; COMB Node = 'vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|cpu_data_master_qualified_request_cfi_flash_s1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.331 ns" { vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1~102 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1 } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6321 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.386 ns) + CELL(0.706 ns) 5.481 ns vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|Add2~171 6 COMB LCCOMB_X33_Y17_N14 2 " "Info: 6: + IC(0.386 ns) + CELL(0.706 ns) = 5.481 ns; Loc. = LCCOMB_X33_Y17_N14; Fanout = 2; COMB Node = 'vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|Add2~171'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.092 ns" { vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~171 } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6842 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.567 ns vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|Add2~173 7 COMB LCCOMB_X33_Y17_N16 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 5.567 ns; Loc. = LCCOMB_X33_Y17_N16; Fanout = 2; COMB Node = 'vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|Add2~173'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~171 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~173 } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6842 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.653 ns vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|Add2~175 8 COMB LCCOMB_X33_Y17_N18 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 5.653 ns; Loc. = LCCOMB_X33_Y17_N18; Fanout = 2; COMB Node = 'vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|Add2~175'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~173 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~175 } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6842 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 6.159 ns vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|Add2~176 9 COMB LCCOMB_X33_Y17_N20 3 " "Info: 9: + IC(0.000 ns) + CELL(0.506 ns) = 6.159 ns; Loc. = LCCOMB_X33_Y17_N20; Fanout = 3; COMB Node = 'vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|Add2~176'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~175 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~176 } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6842 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.068 ns) + CELL(0.206 ns) 7.433 ns vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|tristate_bridge_avalon_slave_grant_vector\[0\]~161 10 COMB LCCOMB_X29_Y17_N28 8 " "Info: 10: + IC(1.068 ns) + CELL(0.206 ns) = 7.433 ns; Loc. = LCCOMB_X29_Y17_N28; Fanout = 8; COMB Node = 'vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|tristate_bridge_avalon_slave_grant_vector\[0\]~161'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.274 ns" { vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~176 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_avalon_slave_grant_vector[0]~161 } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6484 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.206 ns) 8.047 ns vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|p1_tristate_bridge_address\[24\]~1448 11 COMB LCCOMB_X29_Y17_N8 24 " "Info: 11: + IC(0.408 ns) + CELL(0.206 ns) = 8.047 ns; Loc. = LCCOMB_X29_Y17_N8; Fanout = 24; COMB Node = 'vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|p1_tristate_bridge_address\[24\]~1448'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.614 ns" { vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_avalon_slave_grant_vector[0]~161 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|p1_tristate_bridge_address[24]~1448 } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6459 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.209 ns) + CELL(0.206 ns) 11.462 ns vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|p1_tristate_bridge_address\[21\]~1452 12 COMB LCCOMB_X1_Y2_N20 1 " "Info: 12: + IC(3.209 ns) + CELL(0.206 ns) = 11.462 ns; Loc. = LCCOMB_X1_Y2_N20; Fanout = 1; COMB Node = 'vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|p1_tristate_bridge_address\[21\]~1452'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.415 ns" { vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|p1_tristate_bridge_address[24]~1448 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|p1_tristate_bridge_address[21]~1452 } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6459 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.637 ns) + CELL(0.509 ns) 12.608 ns vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|tristate_bridge_address\[21\] 13 REG IOC_X0_Y2_N1 1 " "Info: 13: + IC(0.637 ns) + CELL(0.509 ns) = 12.608 ns; Loc. = IOC_X0_Y2_N1; Fanout = 1; REG Node = 'vga_sys:inst1\|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave\|tristate_bridge_address\[21\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.146 ns" { vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|p1_tristate_bridge_address[21]~1452 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 6930 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.916 ns ( 31.06 % ) " "Info: Total cell delay = 3.916 ns ( 31.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.692 ns ( 68.94 % ) " "Info: Total interconnect delay = 8.692 ns ( 68.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.608 ns" { vga_sys:inst1|cpu:the_cpu|i_read vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_instruction_master_arbiterlock~29 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1~101 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1~102 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~171 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~173 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~175 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~176 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_avalon_slave_grant_vector[0]~161 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|p1_tristate_bridge_address[24]~1448 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|p1_tristate_bridge_address[21]~1452 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.608 ns" { vga_sys:inst1|cpu:the_cpu|i_read {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_instruction_master_arbiterlock~29 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1~101 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1~102 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~171 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~173 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~175 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~176 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_avalon_slave_grant_vector[0]~161 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|p1_tristate_bridge_address[24]~1448 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|p1_tristate_bridge_address[21]~1452 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] {} } { 0.000ns 1.115ns 0.374ns 0.370ns 1.125ns 0.386ns 0.000ns 0.000ns 0.000ns 1.068ns 0.408ns 3.209ns 0.637ns } { 0.000ns 0.623ns 0.206ns 0.370ns 0.206ns 0.706ns 0.086ns 0.086ns 0.506ns 0.206ns 0.206ns 0.206ns 0.509ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.017 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.017 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} altpll0:inst|altpll:altpll_component|_clk0~clkctrl {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] {} } { 0.000ns 1.373ns 1.310ns } { 0.000ns 0.000ns 0.334ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.212 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|cpu:the_cpu|i_read } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.212 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} altpll0:inst|altpll:altpll_component|_clk0~clkctrl {} vga_sys:inst1|cpu:the_cpu|i_read {} } { 0.000ns 1.373ns 1.173ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.608 ns" { vga_sys:inst1|cpu:the_cpu|i_read vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_instruction_master_arbiterlock~29 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1~101 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1~102 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~171 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~173 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~175 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~176 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_avalon_slave_grant_vector[0]~161 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|p1_tristate_bridge_address[24]~1448 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|p1_tristate_bridge_address[21]~1452 vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.608 ns" { vga_sys:inst1|cpu:the_cpu|i_read {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_instruction_master_arbiterlock~29 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1~101 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1~102 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|cpu_data_master_qualified_request_cfi_flash_s1 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~171 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~173 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~175 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|Add2~176 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_avalon_slave_grant_vector[0]~161 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|p1_tristate_bridge_address[24]~1448 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|p1_tristate_bridge_address[21]~1452 {} vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21] {} } { 0.000ns 1.115ns 0.374ns 0.370ns 1.125ns 0.386ns 0.000ns 0.000ns 0.000ns 1.068ns 0.408ns 3.209ns 0.637ns } { 0.000ns 0.623ns 0.206ns 0.370ns 0.206ns 0.706ns 0.086ns 0.086ns 0.506ns 0.206ns 0.206ns 0.206ns 0.509ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "altpll0:inst\|altpll:altpll_component\|_clk1 " "Info: No valid register-to-register data paths exist for clock \"altpll0:inst\|altpll:altpll_component\|_clk1\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk2 register vga_sys:inst1\|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch\|data_out register vga_sys:inst1\|freedev_vga_inst:the_freedev_vga_inst\|freedev_vga:the_freedev_vga\|line_addr\[22\] 8.799 ns " "Info: Slack time is 8.799 ns for clock \"altpll0:inst\|altpll:altpll_component\|_clk2\" between source register \"vga_sys:inst1\|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch\|data_out\" and destination register \"vga_sys:inst1\|freedev_vga_inst:the_freedev_vga_inst\|freedev_vga:the_freedev_vga\|line_addr\[22\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "13.077 ns + Largest register register " "Info: + Largest register to register requirement is 13.077 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "13.333 ns + " "Info: + Setup relationship between source and destination is 13.333 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 23.856 ns " "Info: + Latch edge is 23.856 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst\|altpll:altpll_component\|_clk2 40.000 ns -2.810 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst\|altpll:altpll_component\|_clk2\" is 40.000 ns with  offset of -2.810 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 10.523 ns " "Info: - Launch edge is 10.523 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst\|altpll:altpll_component\|_clk0 13.333 ns -2.810 ns  50 " "Info: Clock period of Source clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" is 13.333 ns with  offset of -2.810 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.008 ns + Largest " "Info: + Largest clock skew is 0.008 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk2 destination 3.216 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll0:inst\|altpll:altpll_component\|_clk2\" to destination register is 3.216 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst\|altpll:altpll_component\|_clk2 1 CLK PLL_2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll0:inst\|altpll:altpll_component\|_clk2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst|altpll:altpll_component|_clk2 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 894 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.373 ns) + CELL(0.000 ns) 1.373 ns altpll0:inst\|altpll:altpll_component\|_clk2~clkctrl 2 COMB CLKCTRL_G6 215 " "Info: 2: + IC(1.373 ns) + CELL(0.000 ns) = 1.373 ns; Loc. = CLKCTRL_G6; Fanout = 215; COMB Node = 'altpll0:inst\|altpll:altpll_component\|_clk2~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.373 ns" { altpll0:inst|altpll:altpll_component|_clk2 altpll0:inst|altpll:altpll_component|_clk2~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 894 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.177 ns) + CELL(0.666 ns) 3.216 ns vga_sys:inst1\|freedev_vga_inst:the_freedev_vga_inst\|freedev_vga:the_freedev_vga\|line_addr\[22\] 3 REG LCFF_X43_Y21_N11 4 " "Info: 3: + IC(1.177 ns) + CELL(0.666 ns) = 3.216 ns; Loc. = LCFF_X43_Y21_N11; Fanout = 4; REG Node = 'vga_sys:inst1\|freedev_vga_inst:the_freedev_vga_inst\|freedev_vga:the_freedev_vga\|line_addr\[22\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.843 ns" { altpll0:inst|altpll:altpll_component|_clk2~clkctrl vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] } "NODE_NAME" } } { "freedev_vga/freedev_vga.v" "" { Text "D:/FreeDevDAV/example/vga_system/freedev_vga/freedev_vga.v" 307 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 20.71 % ) " "Info: Total cell delay = 0.666 ns ( 20.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.550 ns ( 79.29 % ) " "Info: Total interconnect delay = 2.550 ns ( 79.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.216 ns" { altpll0:inst|altpll:altpll_component|_clk2 altpll0:inst|altpll:altpll_component|_clk2~clkctrl vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.216 ns" { altpll0:inst|altpll:altpll_component|_clk2 {} altpll0:inst|altpll:altpll_component|_clk2~clkctrl {} vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] {} } { 0.000ns 1.373ns 1.177ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 source 3.208 ns - Longest register " "Info: - Longest clock path from clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" to source register is 3.208 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll0:inst\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.373 ns) + CELL(0.000 ns) 1.373 ns altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G7 3896 " "Info: 2: + IC(1.373 ns) + CELL(0.000 ns) = 1.373 ns; Loc. = CLKCTRL_G7; Fanout = 3896; COMB Node = 'altpll0:inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.373 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.169 ns) + CELL(0.666 ns) 3.208 ns vga_sys:inst1\|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch\|data_out 3 REG LCFF_X50_Y29_N19 57 " "Info: 3: + IC(1.169 ns) + CELL(0.666 ns) = 3.208 ns; Loc. = LCFF_X50_Y29_N19; Fanout = 57; REG Node = 'vga_sys:inst1\|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch\|data_out'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.835 ns" { altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7256 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 20.76 % ) " "Info: Total cell delay = 0.666 ns ( 20.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.542 ns ( 79.24 % ) " "Info: Total interconnect delay = 2.542 ns ( 79.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.208 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.208 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} altpll0:inst|altpll:altpll_component|_clk0~clkctrl {} vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out {} } { 0.000ns 1.373ns 1.169ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.216 ns" { altpll0:inst|altpll:altpll_component|_clk2 altpll0:inst|altpll:altpll_component|_clk2~clkctrl vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.216 ns" { altpll0:inst|altpll:altpll_component|_clk2 {} altpll0:inst|altpll:altpll_component|_clk2~clkctrl {} vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] {} } { 0.000ns 1.373ns 1.177ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.208 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.208 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} altpll0:inst|altpll:altpll_component|_clk0~clkctrl {} vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out {} } { 0.000ns 1.373ns 1.169ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7256 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" {  } { { "freedev_vga/freedev_vga.v" "" { Text "D:/FreeDevDAV/example/vga_system/freedev_vga/freedev_vga.v" 307 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.216 ns" { altpll0:inst|altpll:altpll_component|_clk2 altpll0:inst|altpll:altpll_component|_clk2~clkctrl vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.216 ns" { altpll0:inst|altpll:altpll_component|_clk2 {} altpll0:inst|altpll:altpll_component|_clk2~clkctrl {} vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] {} } { 0.000ns 1.373ns 1.177ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.208 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.208 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} altpll0:inst|altpll:altpll_component|_clk0~clkctrl {} vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out {} } { 0.000ns 1.373ns 1.169ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.278 ns - Longest register register " "Info: - Longest register to register delay is 4.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_sys:inst1\|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch\|data_out 1 REG LCFF_X50_Y29_N19 57 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X50_Y29_N19; Fanout = 57; REG Node = 'vga_sys:inst1\|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch\|data_out'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out } "NODE_NAME" } } { "vga_sys.v" "" { Text "D:/FreeDevDAV/example/vga_system/vga_sys.v" 7256 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns vga_sys:inst1\|freedev_vga_inst:the_freedev_vga_inst\|freedev_vga:the_freedev_vga\|line_addr\[9\]~2287 2 COMB LCCOMB_X50_Y29_N18 18 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X50_Y29_N18; Fanout = 18; COMB Node = 'vga_sys:inst1\|freedev_vga_inst:the_freedev_vga_inst\|freedev_vga:the_freedev_vga\|line_addr\[9\]~2287'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[9]~2287 } "NODE_NAME" } } { "freedev_vga/freedev_vga.v" "" { Text "D:/FreeDevDAV/example/vga_system/freedev_vga/freedev_vga.v" 307 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.030 ns) + CELL(0.855 ns) 4.278 ns vga_sys:inst1\|freedev_vga_inst:the_freedev_vga_inst\|freedev_vga:the_freedev_vga\|line_addr\[22\] 3 REG LCFF_X43_Y21_N11 4 " "Info: 3: + IC(3.030 ns) + CELL(0.855 ns) = 4.278 ns; Loc. = LCFF_X43_Y21_N11; Fanout = 4; REG Node = 'vga_sys:inst1\|freedev_vga_inst:the_freedev_vga_inst\|freedev_vga:the_freedev_vga\|line_addr\[22\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.885 ns" { vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[9]~2287 vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] } "NODE_NAME" } } { "freedev_vga/freedev_vga.v" "" { Text "D:/FreeDevDAV/example/vga_system/freedev_vga/freedev_vga.v" 307 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.248 ns ( 29.17 % ) " "Info: Total cell delay = 1.248 ns ( 29.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.030 ns ( 70.83 % ) " "Info: Total interconnect delay = 3.030 ns ( 70.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.278 ns" { vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[9]~2287 vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.278 ns" { vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out {} vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[9]~2287 {} vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] {} } { 0.000ns 0.000ns 3.030ns } { 0.000ns 0.393ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.216 ns" { altpll0:inst|altpll:altpll_component|_clk2 altpll0:inst|altpll:altpll_component|_clk2~clkctrl vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.216 ns" { altpll0:inst|altpll:altpll_component|_clk2 {} altpll0:inst|altpll:altpll_component|_clk2~clkctrl {} vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] {} } { 0.000ns 1.373ns 1.177ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.208 ns" { altpll0:inst|altpll:altpll_component|_clk0 altpll0:inst|altpll:altpll_component|_clk0~clkctrl vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.208 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} altpll0:inst|altpll:altpll_component|_clk0~clkctrl {} vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out {} } { 0.000ns 1.373ns 1.169ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.278 ns" { vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[9]~2287 vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.278 ns" { vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out {} vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[9]~2287 {} vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22] {} } { 0.000ns 0.000ns 3.030ns } { 0.000ns 0.393ns 0.855ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}