vga_system.map.rpt

来自「verilog代码读写SDRAM 不带仿真」· RPT 代码 · 共 406 行 · 第 1/5 页

; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; Parallel Synthesis                                                             ; Off                ; Off                ;
; DSP Block Balancing                                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                       ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                       ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; vga_system.bdf                   ; yes             ; User Block Diagram/Schematic File  ; D:/FreeDevDAV/example/vga_system/vga_system.bdf                    ;
; freedev_vga/freedev_vga.v        ; yes             ; User Verilog HDL File              ; D:/FreeDevDAV/example/vga_system/freedev_vga/freedev_vga.v         ;
; altpll0.v                        ; yes             ; Other                              ; D:/FreeDevDAV/example/vga_system/altpll0.v                         ;
; altpll.tdf                       ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/altpll.tdf            ;
; aglobal72.inc                    ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/aglobal72.inc         ;
; stratix_pll.inc                  ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/stratix_pll.inc       ;
; stratixii_pll.inc                ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/stratixii_pll.inc     ;
; cycloneii_pll.inc                ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/cycloneii_pll.inc     ;
; vga_sys.v                        ; yes             ; Other                              ; D:/FreeDevDAV/example/vga_system/vga_sys.v                         ;
; burst_0.v                        ; yes             ; Other                              ; D:/FreeDevDAV/example/vga_system/burst_0.v                         ;
; cpu.v                            ; yes             ; Other                              ; D:/FreeDevDAV/example/vga_system/cpu.v                             ;
; cpu_test_bench.v                 ; yes             ; Other                              ; D:/FreeDevDAV/example/vga_system/cpu_test_bench.v                  ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/lpm_decode.inc        ;
; a_rdenreg.inc                    ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                       ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/altrom.inc            ;
; altram.inc                       ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/altram.inc            ;
; altdpram.inc                     ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/altdpram.inc          ;
; altqpram.inc                     ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_cub1.tdf           ; yes             ; Auto-Generated Megafunction        ; D:/FreeDevDAV/example/vga_system/db/altsyncram_cub1.tdf            ;
; db/altsyncram_k1l1.tdf           ; yes             ; Auto-Generated Megafunction        ; D:/FreeDevDAV/example/vga_system/db/altsyncram_k1l1.tdf            ;