vga_system.map.rpt

来自「verilog代码读写SDRAM 不带仿真」· RPT 代码 · 共 406 行 · 第 1/5 页

 75. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a
 76. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram
 77. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b
 78. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram
 79. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag
 80. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_dc_tag_module:cpu_dc_tag|altsyncram:the_altsyncram
 81. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data
 82. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_dc_data_module:cpu_dc_data|altsyncram:the_altsyncram
 83. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim
 84. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_dc_victim_module:cpu_dc_victim|altsyncram:the_altsyncram
 85. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1
 86. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2
 87. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component
 88. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 89. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component
 90. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 91. Parameter Settings for User Entity Instance: vga_sys:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1
 92. Parameter Settings for User Entity Instance: vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga
 93. Parameter Settings for User Entity Instance: vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|vga_fifo:line_fifo|dcfifo:dcfifo_component
 94. Parameter Settings for User Entity Instance: vga_sys:inst1|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo
 95. Parameter Settings for User Entity Instance: vga_sys:inst1|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo
 96. Parameter Settings for User Entity Instance: vga_sys:inst1|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic
 97. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 98. altmult_add Parameter Settings by Entity Instance
 99. dcfifo Parameter Settings by Entity Instance
100. scfifo Parameter Settings by Entity Instance
101. Analysis & Synthesis Messages



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+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sat Mar 01 10:38:25 2008         ;
; Quartus II Version                 ; 7.2 Build 203 02/05/2008 SP 2 SJ Full Version ;
; Revision Name                      ; vga_system                                    ;
; Top-level Entity Name              ; vga_system                                    ;
; Family                             ; Cyclone II                                    ;
; Total logic elements               ; 4,629                                         ;
;     Total combinational functions  ; 4,629                                         ;
;     Dedicated logic registers      ; 3,045                                         ;
; Total registers                    ; 3045                                          ;
; Total pins                         ; 129                                           ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 90,048                                        ;
; Embedded Multiplier 9-bit elements ; 4                                             ;
; Total PLLs                         ; 1                                             ;
+------------------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP2C35F484C8       ;                    ;
; Top-level entity name                                                          ; vga_system         ; vga_system         ;
; Family name                                                                    ; Cyclone II         ; Stratix II         ;
; Optimization Technique -- Cyclone II/Cyclone III                               ; Speed              ; Balanced           ;
; Use Generated Physical Constraints File                                        ; Off                ;                    ;
; Use smart compilation                                                          ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation                            ; 1                  ; 1                  ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;