bt656_detection.v

verilog代码读写SDRAM 不带仿真

//---------------------------------------------------------------
//模块名称：bt656_detection
//功能说明：BT656视频参数检测模块
//	    读BT656视频数据,检测相关参数
//日    期：20070906
//备    注：
//	1、视频参数检测
//
//公司：杭州自由电子科技
//电话：[phone]
//网址：www.freefpga.com
//邮件：[e-mail]
//----------------------------------------------------------------

module bt656_detection(
	// BT656视频信号
	v_clk,
	v_data,
	
	// BT656 相关参数
	count_8010,	
	count_ycbcr,
	count_total,
	line_total,
	odd_line,
	even_line
	);
	
	//视频信号
	input v_clk;			// 视频数据时钟
	input [7:0]v_data;		// 8bit YCbCr视频数据
	
	// BT656 相关参数
	output [31:0]count_8010;	//BLANKING 部分8010计数	
	output [31:0]count_ycbcr;	//图象数据 部分计数
	output [31:0]count_total;	//一行数据字节计数
	output [31:0]line_total;	// 总行数
	output [31:0]odd_line;		// 奇场行数
	output [31:0]even_line;		// 偶场行数

/////////////////////////// bt656视频数据参数检测 ////////////////////////////////////////////////

	reg [31:0]count_8010;
	reg [31:0]count_ycbcr;
	reg [31:0]count_total;
	
	reg [31:0]tmp_8010;
	reg [31:0]tmp_ycbcr;
	reg [31:0]tmp_total;

	reg	[7:0]RR1,RR2,RR3;
	
	always @(posedge v_clk)
	begin
		RR1 <= #1 v_data;
		RR2 <= #1 RR1;
		RR3 <= #1 RR2;
	end
	
	// EAV SAV CODE检测
	wire av_flag = (( RR3 == 8'hff) && ( RR2 == 8'h00 ) && ( RR1 == 8'h00)) ? 1 : 0;
	
	// SAV and EAV 
	reg [2:0] previous_fvh,fvh;
		
	wire f_flag = v_data[6];	// field flag
	wire v_flag = v_data[5];	// blanking flag
	wire h_flag = v_data[4];	// h=0 at SAV , h=1 at EAV
	
	reg blanking;	// 消隐信号
	
	// 行信号参数检测
	always @(posedge v_clk)
	if ( av_flag == 1'b1) 
	begin
		if(h_flag == 1'b1)	// EAV
		begin
			tmp_8010 <= #1 32'h00000000;
			count_ycbcr <= #1 tmp_ycbcr - 3;
			
			blanking <= #1 1'b1;
			
		end else begin		// SAV
			count_8010 <= #1 tmp_8010 - 3;
			tmp_ycbcr<= #1 32'h00000000;
			count_total <= count_ycbcr + count_8010 + 32'h00000008;
			
			blanking <= #1 1'b0;
		end	
		
			
	end else begin 
		tmp_8010 <= #1 tmp_8010 + 32'h00000001;
		tmp_ycbcr <= #1 tmp_ycbcr + 32'h00000001;
		
	end
	
	// 场相关参数检测
	reg [31:0]total_line;
	reg [31:0]line;
	reg [31:0]odd_line;
	reg [31:0]even_line;
	
	wire [1:0]odd_even={fvh[2],v_data[6]};
	
	always @(posedge v_clk)
	if ( av_flag == 1'b1 && h_flag == 1'b1) 		// EAV 期间
	begin
		fvh 	     <= v_data[6:4];
	
		case (odd_even)
			2'b10: begin
				total_line <= line;		//奇偶场总行数
				line <= 32'h00000000;		//奇场，行开始
				even_line <= line;
			end
			2'b01: begin
				odd_line <= line;
				line <= line +1;	
			end 
			default: line<= line +1;
		endcase
		
	
	end 
	
	     
endmodule