vga_system.tan.summary

来自「verilog代码读写SDRAM 不带仿真」· SUMMARY 代码 · 共 107 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.847 ns
From           : altera_internal_jtag~RUNIDLEUSER
To             : vga_sys:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|monitor_go
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.296 ns
From           : vga_sys:inst1|led_pio:the_led_pio|data_out[1]
To             : LED[1]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 3.026 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.932 ns
From           : altera_internal_jtag~TDIUTAP
To             : sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'altpll0:inst|altpll:altpll_component|_clk0'
Slack          : 0.125 ns
Required Time  : 75.00 MHz ( period = 13.333 ns )
Actual Time    : 75.71 MHz ( period = 13.208 ns )
From           : vga_sys:inst1|cpu:the_cpu|i_read
To             : vga_sys:inst1|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|tristate_bridge_address[21]
From Clock     : altpll0:inst|altpll:altpll_component|_clk0
To Clock       : altpll0:inst|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altpll0:inst|altpll:altpll_component|_clk2'
Slack          : 8.799 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : vga_sys:inst1|vga_sys_reset_clk_domain_synch_module:vga_sys_reset_clk_domain_synch|data_out
To             : vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|line_addr[22]
From Clock     : altpll0:inst|altpll:altpll_component|_clk0
To Clock       : altpll0:inst|altpll:altpll_component|_clk2
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 92.18 MHz ( period = 10.848 ns )
From           : vga_sys:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[0]
To             : sld_hub:sld_hub_inst|hub_tdo_reg
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'altpll0:inst|altpll:altpll_component|_clk0'
Slack          : 0.499 ns
Required Time  : 75.00 MHz ( period = 13.333 ns )
Actual Time    : N/A
From           : vga_sys:inst1|sdram:the_sdram|i_cmd[4]
To             : vga_sys:inst1|sdram:the_sdram|i_cmd[4]
From Clock     : altpll0:inst|altpll:altpll_component|_clk0
To Clock       : altpll0:inst|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'altpll0:inst|altpll:altpll_component|_clk2'
Slack          : 0.739 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|vga_fifo:line_fifo|dcfifo:dcfifo_component|dcfifo_min1:auto_generated|alt_synch_pipe_0e8:rs_dgwp|dffpipe_qe9:dffpipe7|dffe8a[7]
To             : vga_sys:inst1|freedev_vga_inst:the_freedev_vga_inst|freedev_vga:the_freedev_vga|vga_fifo:line_fifo|dcfifo:dcfifo_component|dcfifo_min1:auto_generated|alt_synch_pipe_0e8:rs_dgwp|dffpipe_qe9:dffpipe7|dffe9a[7]
From Clock     : altpll0:inst|altpll:altpll_component|_clk2
To Clock       : altpll0:inst|altpll:altpll_component|_clk2
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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