vga_sys.ptf.pre_generation_ptf
来自「verilog代码读写SDRAM 不带仿真」· PRE_GENERATION_PTF 代码 · 共 2,072 行 · 第 1/4 页
PRE_GENERATION_PTF
2,072 行
class_version = "7.2";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
}
MODULE cfi_flash
{
SLAVE s1
{
PORT_WIRING
{
PORT data
{
type = "data";
width = "16";
direction = "inout";
Is_Enabled = "1";
is_shared = "1";
}
PORT address
{
type = "address";
width = "24";
direction = "input";
Is_Enabled = "1";
is_shared = "1";
}
PORT read_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "1";
}
PORT select_n
{
type = "chipselect_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Write_Wait_States = "160ns";
Read_Wait_States = "160ns";
Hold_Time = "40ns";
Setup_Time = "40ns";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "1";
Address_Span = "33554432";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Active_CS_Through_Read_Latency = "0";
Data_Width = "16";
Address_Width = "24";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY tristate_bridge/tristate_master
{
priority = "1";
Offset_Address = "0x00000000";
}
Base_Address = "0x00000000";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Setup_Value = "40";
Wait_Value = "160";
Hold_Value = "40";
Timing_Units = "ns";
Unit_Multiplier = "1";
Size = "33554432";
}
SYSTEM_BUILDER_INFO
{
Simulation_Num_Lanes = "2";
Is_Enabled = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
class = "altera_avalon_cfi_flash";
class_version = "7.2";
}
MODULE freedev_vga_inst
{
SLAVE avalon_slave_0
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT rst_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT s_irq
{
type = "irq";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT s_chipselect_n
{
type = "chipselect_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT s_read_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT s_write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT s_address
{
type = "address";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT s_readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT s_writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "64";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "4";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02101000";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "2";
}
Base_Address = "0x02101000";
}
}
MASTER avalon_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "1";
Do_Stream_Writes = "1";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "32";
Maximum_Burst_Size = "128";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
}
PORT_WIRING
{
PORT m_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT m_address
{
type = "address";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT m_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT m_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT m_write
{
type = "write";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT m_writedata
{
type = "writedata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT m_byteenable
{
type = "byteenable";
width = "4";
direction = "output";
Is_Enabled = "1";
}
PORT m_burstcount
{
type = "burstcount";
width = "8";
direction = "output";
Is_Enabled = "1";
}
PORT m_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
MEMORY_MAP
{
Entry sdram/s1
{
address = "0x08000000";
span = "0x04000000";
}
}
}
PORT_WIRING
{
PORT pclk
{
type = "export";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT r
{
type = "export";
width = "8";
direction = "output";
Is_Enabled = "1";
}
PORT g
{
type = "export";
width = "8";
direction = "output";
Is_Enabled = "1";
}
PORT b
{
type = "export";
width = "8";
direction = "output";
Is_Enabled = "1";
}
PORT hsync
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT vsync
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT blank
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT sync
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT psave
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
class = "no_legacy_module";
class_version = "1.0";
gtf_class_name = "freedev_vga";
gtf_class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Do_Not_Generate = "1";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
HDL_INFO
{
Simulation_HDL_Files = "D:\\FreeDevDAV\\example\\vga_system/freedev_vga_inst.v";
}
}
MODULE freedev_sram_0
{
SLAVE avalon_tristate_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Write_Wait_States = "0ns";
Read_Wait_States = "0ns";
Hold_Time = "5ns";
Setup_Time = "10ns";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "524288";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Active_CS_Through_Read_Latency = "0";
Data_Width = "16";
Address_Width = "18";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY tristate_bridge/tristate_master
{
priority = "1";
Offset_Address = "0x02080000";
}
Base_Address = "0x02080000";
}
PORT_WIRING
{
PORT address
{
type = "address";
width = "18";
direction = "input";
Is_Enabled = "1";
is_shared = "1";
}
PORT data
{
type = "data";
width = "16";
direction = "inout";
Is_Enabled = "1";
is_shared = "1";
}
PORT be
{
type = "byteenable_n";
width = "2";
direction = "input";
Is_Enabled = "1";
is_shared = "1";
}
PORT oe
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT we
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT ce
{
type = "chipselect_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
}
}
class = "freedev_sram";
class_version = "1.0";
COMPONENT_BUILDER
{
GLS_SETTINGS
{
}
}
WIZARD_SCRIPT_ARGUMENTS
{
hdl_parameters
{
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
}
}
}
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