vga_sys.ptf.pre_generation_ptf
来自「verilog代码读写SDRAM 不带仿真」· PRE_GENERATION_PTF 代码 · 共 2,072 行 · 第 1/4 页
PRE_GENERATION_PTF
2,072 行
Accepts_Internal_Connections = "1";
Data_Width = "16";
Address_Width = "25";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
Offset_Address = "0x08000000";
}
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x08000000";
}
MASTERED_BY freedev_vga_inst/avalon_master
{
priority = "1";
Offset_Address = "0x08000000";
}
Base_Address = "0x08000000";
}
}
PORT_WIRING
{
PORT zs_addr
{
type = "zs_addr";
width = "13";
direction = "output";
Is_Enabled = "1";
}
PORT zs_ba
{
type = "zs_ba";
width = "2";
direction = "output";
Is_Enabled = "1";
}
PORT zs_cas_n
{
type = "zs_cas_n";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT zs_cke
{
type = "zs_cke";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT zs_cs_n
{
type = "zs_cs_n";
width = "2";
direction = "output";
Is_Enabled = "1";
}
PORT zs_dq
{
type = "zs_dq";
width = "16";
direction = "output";
Is_Enabled = "1";
}
PORT zs_dqm
{
type = "zs_dqm";
width = "2";
direction = "output";
Is_Enabled = "1";
}
PORT zs_ras_n
{
type = "zs_ras_n";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT zs_we_n
{
type = "zs_we_n";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
iss_model_name = "altera_memory";
WIZARD_SCRIPT_ARGUMENTS
{
register_data_in = "1";
sim_model_base = "1";
sdram_data_width = "16";
sdram_addr_width = "13";
sdram_row_width = "13";
sdram_col_width = "9";
sdram_num_chipselects = "2";
sdram_num_banks = "4";
refresh_period = "15.625";
powerup_delay = "100.0";
cas_latency = "3";
t_rfc = "70.0";
t_rp = "20.0";
t_mrd = "3";
t_rcd = "20.0";
t_ac = "5.5";
t_wr = "14.0";
init_refresh_commands = "2";
init_nop_delay = "0.0";
shared_data = "0";
sdram_bank_width = "2";
tristate_bridge_slave = "";
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "az_addr";
radix = "hexadecimal";
}
SIGNAL b
{
name = "az_be_n";
}
SIGNAL c
{
name = "az_cs";
}
SIGNAL d
{
name = "az_data";
radix = "hexadecimal";
}
SIGNAL e
{
name = "az_rd_n";
}
SIGNAL f
{
name = "az_wr_n";
}
SIGNAL h
{
name = "za_data";
radix = "hexadecimal";
}
SIGNAL i
{
name = "za_valid";
}
SIGNAL j
{
name = "za_waitrequest";
}
SIGNAL l
{
name = "CODE";
radix = "ascii";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "sdram";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
class = "altera_avalon_new_sdram_controller";
class_version = "7.2";
}
MODULE sys_clk_timer
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT irq
{
type = "irq";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "3";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "16";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "16";
direction = "output";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "16";
Address_Width = "3";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02101040";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "1";
}
Base_Address = "0x02101040";
}
}
class = "altera_avalon_timer";
class_version = "7.2";
iss_model_name = "altera_avalon_timer";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Top_Level_Ports_Are_Enumerated = "1";
View
{
Settings_Summary = "Timer with 20.0 ms timeout period.";
Is_Collapsed = "1";
}
Clock_Source = "clk";
Has_Clock = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
always_run = "0";
fixed_period = "0";
snapshot = "1";
period = "20.0";
period_units = "ms";
reset_output = "0";
timeout_pulse_output = "0";
load_value = "1499999";
}
}
MODULE led_pio
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "4";
Address_Width = "2";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02101060";
}
Base_Address = "0x02101060";
}
}
PORT_WIRING
{
PORT out_port
{
type = "export";
width = "4";
direction = "output";
Is_Enabled = "1";
}
}
class = "altera_avalon_pio";
class_version = "7.2";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
Data_Width = "4";
edge_type = "NONE";
irq_type = "NONE";
bit_clearing_edge_register = "0";
}
}
MODULE tristate_bridge
{
SLAVE avalon_slave
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "1";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "1";
Register_Outgoing_Signals = "1";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
Offset_Address = "0x00000000";
}
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x00000000";
}
}
}
MASTER tristate_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
}
PORT_WIRING
{
}
MEMORY_MAP
{
Entry cfi_flash/s1
{
address = "0x00000000";
span = "0x02000000";
}
Entry freedev_sram_0/avalon_tristate_slave_0
{
address = "0x02080000";
span = "0x00080000";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
}
class = "altera_avalon_tri_state_bridge";
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