cpu.v

verilog代码读写SDRAM 不带仿真

                begin
                  dbrk1[65] <= jdo[23];
                  dbrk1[66] <= jdo[24];
                  dbrk1[67] <= jdo[25];
                  dbrk1[68] <= jdo[26];
                  dbrk1[69] <= jdo[27];
                  dbrk1[70] <= jdo[28];
                  if (1)
                      dbrk1[64] <= jdo[22];
                  if (1)
                    begin
                      dbrk1[71] <= jdo[29];
                      dbrk1[72] <= jdo[30];
                      dbrk1[73] <= jdo[31];
                    end
                  dbrk1[74] <= jdo[21];
                  dbrk1[75] <= jdo[20];
                  dbrk1[76] <= jdo[19];
                  dbrk1[77] <= jdo[18];
                end
              if ((0 >= 3) && (break_c_rr == 2'b10))
                begin
                  dbrk2[65] <= jdo[23];
                  dbrk2[66] <= jdo[24];
                  dbrk2[67] <= jdo[25];
                  dbrk2[68] <= jdo[26];
                  dbrk2[69] <= jdo[27];
                  dbrk2[70] <= jdo[28];
                  if (1)
                      dbrk2[64] <= jdo[22];
                  if (1)
                    begin
                      dbrk2[71] <= jdo[29];
                      dbrk2[72] <= jdo[30];
                      dbrk2[73] <= jdo[31];
                    end
                  dbrk2[74] <= jdo[21];
                  dbrk2[75] <= jdo[20];
                  dbrk2[76] <= jdo[19];
                  dbrk2[77] <= jdo[18];
                end
              if ((0 >= 4) && (break_c_rr == 2'b11))
                begin
                  dbrk3[65] <= jdo[23];
                  dbrk3[66] <= jdo[24];
                  dbrk3[67] <= jdo[25];
                  dbrk3[68] <= jdo[26];
                  dbrk3[69] <= jdo[27];
                  dbrk3[70] <= jdo[28];
                  if (1)
                      dbrk3[64] <= jdo[22];
                  if (1)
                    begin
                      dbrk3[71] <= jdo[29];
                      dbrk3[72] <= jdo[30];
                      dbrk3[73] <= jdo[31];
                    end
                  dbrk3[74] <= jdo[21];
                  dbrk3[75] <= jdo[20];
                  dbrk3[76] <= jdo[19];
                  dbrk3[77] <= jdo[18];
                end
            end
        end
    end


  always @(posedge clk)
    begin
      if (take_action_any_break)
        begin
          dbrk_hit0_latch <= 1'b0;
          dbrk_hit1_latch <= 1'b0;
          dbrk_hit2_latch <= 1'b0;
          dbrk_hit3_latch <= 1'b0;
        end
      else 
        begin
          if (dbrk_hit0 & dbrk0[69])
              dbrk_hit0_latch <= 1'b1;
          if (dbrk_hit1 & dbrk1[69])
              dbrk_hit1_latch <= 1'b1;
          if (dbrk_hit2 & dbrk2[69])
              dbrk_hit2_latch <= 1'b1;
          if (dbrk_hit3 & dbrk3[69])
              dbrk_hit3_latch <= 1'b1;
        end
    end


  always @(posedge clk or negedge jrst_n)
    begin
      if (jrst_n == 0)
          break_readreg <= 32'b0;
      else if (take_action_any_break)
          break_readreg <= jdo[31 : 0];
      else if (take_no_action_break_a)
          case (break_a_wpr_high_bits)
          
              2'd0: begin
                  case (break_a_wpr_low_bits) // synthesis full_case
                  
                      2'd0: begin
                          break_readreg <= (0 >= 1) ? xbrk0 : 32'b0;
                      end // 2'd0 
                  
                      2'd1: begin
                          break_readreg <= (0 >= 2) ? xbrk1 : 32'b0;
                      end // 2'd1 
                  
                      2'd2: begin
                          break_readreg <= (0 >= 3) ? xbrk2 : 32'b0;
                      end // 2'd2 
                  
                      2'd3: begin
                          break_readreg <= (0 >= 4) ? xbrk3 : 32'b0;
                      end // 2'd3 
                  
                  endcase // break_a_wpr_low_bits
              end // 2'd0 
          
              2'd1: begin
                  break_readreg <= 32'b0;
              end // 2'd1 
          
              2'd2: begin
                  case (break_a_wpr_low_bits) // synthesis full_case
                  
                      2'd0: begin
                          break_readreg <= (0 >= 1)  ? 
                                  dbrk0[27 : 0] : 32'b0;
                  
                      end // 2'd0 
                  
                      2'd1: begin
                          break_readreg <= (0 >= 2)  ? 
                                  dbrk1[27 : 0] : 32'b0;
                  
                      end // 2'd1 
                  
                      2'd2: begin
                          break_readreg <= (0 >= 3)  ? 
                                  dbrk2[27 : 0] : 32'b0;
                  
                      end // 2'd2 
                  
                      2'd3: begin
                          break_readreg <= (0 >= 4)  ? 
                                  dbrk3[27 : 0] : 32'b0;
                  
                      end // 2'd3 
                  
                  endcase // break_a_wpr_low_bits
              end // 2'd2 
          
              2'd3: begin
                  case (break_a_wpr_low_bits) // synthesis full_case
                  
                      2'd0: begin
                          break_readreg <= (0 >= 1)  ? 
                                  dbrk0[63 : 32] : 32'b0;
                  
                      end // 2'd0 
                  
                      2'd1: begin
                          break_readreg <= (0 >= 2)  ? 
                                  dbrk1[63 : 32] : 32'b0;
                  
                      end // 2'd1 
                  
                      2'd2: begin
                          break_readreg <= (0 >= 3)  ? 
                                  dbrk2[63 : 32] : 32'b0;
                  
                      end // 2'd2 
                  
                      2'd3: begin
                          break_readreg <= (0 >= 4)  ? 
                                  dbrk3[63 : 32] : 32'b0;
                  
                      end // 2'd3 
                  
                  endcase // break_a_wpr_low_bits
              end // 2'd3 
          
          endcase // break_a_wpr_high_bits
      else if (take_no_action_break_b)
          break_readreg <= jdo[31 : 0];
      else if (take_no_action_break_c)
          break_readreg <= jdo[31 : 0];
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          trigger_state <= 0;
      else if (1)
          if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
              trigger_state <= 0;
          else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
              trigger_state <= -1;
    end


  assign trigger_state_0 = ~trigger_state;
  assign trigger_state_1 = trigger_state;

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_nios2_oci_xbrk (
                            // inputs:
                             D_en,
                             E_en,
                             E_valid,
                             F_pc,
                             M_en,
                             clk,
                             reset_n,
                             trigger_state_0,
                             trigger_state_1,
                             xbrk0,
                             xbrk1,
                             xbrk2,
                             xbrk3,
                             xbrk_ctrl0,
                             xbrk_ctrl1,
                             xbrk_ctrl2,
                             xbrk_ctrl3,

                            // outputs:
                             xbrk_break,
                             xbrk_goto0,
                             xbrk_goto1,
                             xbrk_traceoff,
                             xbrk_traceon,
                             xbrk_trigout
                          )
;

  output           xbrk_break;
  output           xbrk_goto0;
  output           xbrk_goto1;
  output           xbrk_traceoff;
  output           xbrk_traceon;
  output           xbrk_trigout;
  input            D_en;
  input            E_en;
  input            E_valid;
  input   [ 25: 0] F_pc;
  input            M_en;
  input            clk;
  input            reset_n;
  input            trigger_state_0;
  input            trigger_state_1;
  input   [ 27: 0] xbrk0;
  input   [ 27: 0] xbrk1;
  input   [ 27: 0] xbrk2;
  input   [ 27: 0] xbrk3;
  input   [  7: 0] xbrk_ctrl0;
  input   [  7: 0] xbrk_ctrl1;
  input   [  7: 0] xbrk_ctrl2;
  input   [  7: 0] xbrk_ctrl3;

  wire             D_cpu_addr_en;
  wire             E_cpu_addr_en;
  reg              E_xbrk_goto0;
  reg              E_xbrk_goto1;
  reg              E_xbrk_traceoff;
  reg              E_xbrk_traceon;
  reg              E_xbrk_trigout;
  reg              M_xbrk_goto0;
  reg              M_xbrk_goto1;
  reg              M_xbrk_traceoff;
  reg              M_xbrk_traceon;
  reg              M_xbrk_trigout;
  wire    [ 27: 0] cpu_i_address;
  wire             xbrk0_armed;
  wire             xbrk1_armed;
  wire             xbrk2_armed;
  wire             xbrk3_armed;
  reg              xbrk_break;
  wire             xbrk_break_hit;
  wire             xbrk_goto0;
  wire             xbrk_goto0_hit;
  wire             xbrk_goto1;
  wire             xbrk_goto1_hit;
  reg              xbrk_hit0;
  reg              xbrk_hit1;
  reg              xbrk_hit2;
  reg              xbrk_hit3;
  wire             xbrk_toff_hit;
  wire             xbrk_ton_hit;
  wire             xbrk_tout_hit;
  wire             xbrk_traceoff;
  wire             xbrk_traceon;
  wire             xbrk_trigout;
  assign cpu_i_address = {F_pc, 2'b00};
  assign D_cpu_addr_en = D_en;
  assign E_cpu_addr_en = E_en;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          xbrk_hit0 <= 0;
      else if (D_cpu_addr_en)
          xbrk_hit0 <= (0 >= 1) & 
                    (cpu_i_address == xbrk0[27 : 0]);

    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          xbrk_hit1 <= 0;
      else if (D_cpu_addr_en)
          xbrk_hit1 <= (0 >= 2) & 
                    (cpu_i_address == xbrk1[27 : 0]);

    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          xbrk_hit2 <= 0;
      else if (D_cpu_addr_en)
          xbrk_hit2 <= (0 >= 3) & 
                    (cpu_i_address == xbrk2[27 : 0]);

    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          xbrk_hit3 <= 0;
      else if (D_cpu_addr_en)
          xbrk_hit3 <= (0 >= 4) &
                    (cpu_i_address == xbrk3[27 : 0]);

    end


  assign xbrk_break_hit = (xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[0]) | 
    (xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[0]) | 
    (xbrk_hit2 & xbrk2_armed & xbrk_ctrl2[0]) | 
    (xbrk_hit3 & xbrk3_armed & xbrk_ctrl3[0]);

  assign xbrk_ton_hit = (xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[3]) | 
    (xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[3]) | 
    (xbrk_hit2 & xbrk2_armed & xbrk_ctrl2[3]) | 
    (xbrk_hit3 & xbrk3_armed & xbrk_ctrl3[3]);

  assign xbrk_toff_hit = (xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[2]) | 
    (xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[2]) | 
    (xbrk_hit2 & xbrk2_armed & xbrk_ctrl2[2]) | 
    (xbrk_hit3 & xbrk3_armed & xbrk_ctrl3[2]);

  assign xbrk_tout_hit = (xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[1]) | 
    (xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[1]) | 
    (xbrk_hit2 & xbrk2_armed & xbrk_ctrl2[1]) | 
    (xbrk_hit3 & xbrk3_armed & xbrk_ctrl3[1]);

  assign xbrk_goto0_hit = (xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[6]) | 
    (xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[6]) | 
    (xbrk_hit2 & xbrk2_armed & xbrk_ctrl2[6]) | 
    (xbrk_hit3 & xbrk3_armed & xbrk_ctrl3[6]);

  assign xbrk_goto1_hit = (xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[7]) | 
    (xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[7]) | 
    (xbrk_hit2 & xbrk2_armed & xbrk_ctrl2[7]) | 
    (xbrk_hit3 & xbrk3_armed & xbrk_ctrl3[7]);

  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          xbrk_break <= 0;
      else if (E_