📄 cpu.v
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wire [ 31: 0] q;
wire [ 31: 0] ram_q;
wire wrclken;
assign wrclken = 1'b1;
assign q = ram_q;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.clocken0 (wrclken),
.clocken1 (rdclken),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 8,
the_altsyncram.numwords_b = 8,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 3,
the_altsyncram.widthad_b = 3;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (wraddress),
// .address_b (rdaddress),
// .clock0 (wrclock),
// .clock1 (rdclock),
// .clocken0 (wrclken),
// .clocken1 (rdclken),
// .data_a (data),
// .q_b (ram_q),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.address_reg_b = "CLOCK1",
// the_altsyncram.maximum_depth = 0,
// the_altsyncram.numwords_a = 8,
// the_altsyncram.numwords_b = 8,
// the_altsyncram.operation_mode = "DUAL_PORT",
// the_altsyncram.outdata_reg_b = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_b = 32,
// the_altsyncram.widthad_a = 3,
// the_altsyncram.widthad_b = 3;
//
//synthesis read_comments_as_HDL off
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
reg probepresent /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
probepresent <= 1'b0;
resetrequest <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
probepresent <= jdo[19] ? 1
: jdo[18] ? 0
: probepresent;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset)
begin
jtag_break <= probepresent;
resetlatch <= 1;
end
else if (~debugack & debugreq & probepresent)
jtag_break <= 1'b1;
end
always @(posedge clk)
begin
if (take_action_ocimem_a)
begin
monitor_ready <= jdo[25] ? 1'b0 : monitor_ready;
monitor_error <= jdo[25] ? 1'b0 : monitor_error;
monitor_go <= jdo[23] ? 1'b1 : monitor_go;
end
else if (take_action_ocireg)
begin
monitor_ready <= ocireg_mrs ? 1'b1 : monitor_ready;
monitor_error <= ocireg_ers ? 1'b1 : monitor_error;
end
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_ociram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
byteena_a,
clock0,
clock1,
clocken0,
clocken1,
data_a,
data_b,
wren_a,
wren_b,
// outputs:
q_a,
q_b
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q_a;
output [ 31: 0] q_b;
input [ 7: 0] address_a;
input [ 7: 0] address_b;
input [ 3: 0] byteena_a;
input clock0;
input clock1;
input clocken0;
input clocken1;
input [ 31: 0] data_a;
input [ 31: 0] data_b;
input wren_a;
input wren_b;
wire [ 31: 0] q_a;
wire [ 31: 0] q_b;
altsyncram the_altsyncram
(
.address_a (address_a),
.address_b (address_b),
.byteena_a (byteena_a),
.clock0 (clock0),
.clock1 (clock1),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.wren_a (wren_a),
.wren_b (wren_b)
);
defparam the_altsyncram.address_aclr_a = "NONE",
the_altsyncram.address_aclr_b = "NONE",
the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.indata_aclr_a = "NONE",
the_altsyncram.indata_aclr_b = "NONE",
the_altsyncram.init_file = lpm_file,
the_altsyncram.intended_device_family = "Stratix",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.numwords_a = 256,
the_altsyncram.numwords_b = 256,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_aclr_a = "NONE",
the_altsyncram.outdata_aclr_b = "NONE",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8,
the_altsyncram.widthad_b = 8,
the_altsyncram.wrcontrol_aclr_a = "NONE",
the_altsyncram.wrcontrol_aclr_b = "NONE";
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_nios2_ocimem (
// inputs:
address,
begintransfer,
byteenable,
chipselect,
clk,
debugaccess,
jdo,
jrst_n,
resetrequest,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
oci_ram_readdata
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] oci_ram_readdata;
input [ 8: 0] address;
input begintransfer;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input resetrequest;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonRd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonRd1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonWr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon;
wire [ 31: 0] cfgdout;
wire [ 31: 0] oci_ram_readdata;
wire [ 31: 0] sramdout;
assign avalon = begintransfer & ~resetrequest;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
MonWr <= 1'b0;
MonRd <= 1'b0;
MonRd1 <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonAReg[10 : 2]+1;
MonRd <= 1'b1;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
MonRd <= 1'b1;
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonAReg[10 : 2]+1;
MonDReg <= jdo[34 : 3];
MonWr <= 1'b1;
end
else
begin
if (~avalon)
begin
MonWr <= 0;
MonRd <= 0;
end
if (MonRd1)
MonDReg <= MonAReg[10] ? cfgdout : sramdout;
end
MonRd1 <= MonRd;
end
end
//cpu_ociram_lpm_dram_bdp_component, which is an e_bdpram
cpu_ociram_lpm_dram_bdp_component_module cpu_ociram_lpm_dram_bdp_component
(
.address_a (address[7 : 0]),
.address_b (MonAReg[9 : 2]),
.byteena_a (byteenable),
.clock0 (clk),
.clock1 (clk),
.clocken0 (1'b1),
.clocken1 (1'b1),
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