cpu.v

verilog代码读写SDRAM 不带仿真

           the_altsyncram.width_b = 32,
           the_altsyncram.widthad_a = 5,
           the_altsyncram.widthad_b = 5;


//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  altsyncram the_altsyncram
//    (
//      .address_a (wraddress),
//      .address_b (rdaddress),
//      .clock0 (wrclock),
//      .clock1 (rdclock),
//      .clocken0 (wrclken),
//      .clocken1 (rdclken),
//      .data_a (data),
//      .q_b (ram_q),
//      .wren_a (wren)
//    );
//
//  defparam the_altsyncram.address_reg_b = "CLOCK1",
//           the_altsyncram.init_file = lpm_file,
//           the_altsyncram.maximum_depth = 0,
//           the_altsyncram.numwords_a = 32,
//           the_altsyncram.numwords_b = 32,
//           the_altsyncram.operation_mode = "DUAL_PORT",
//           the_altsyncram.outdata_reg_b = "UNREGISTERED",
//           the_altsyncram.ram_block_type = "AUTO",
//           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
//           the_altsyncram.width_a = 32,
//           the_altsyncram.width_b = 32,
//           the_altsyncram.widthad_a = 5,
//           the_altsyncram.widthad_b = 5;
//
//synthesis read_comments_as_HDL off

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_register_bank_b_module (
                                    // inputs:
                                     data,
                                     rdaddress,
                                     rdclken,
                                     rdclock,
                                     wraddress,
                                     wrclock,
                                     wren,

                                    // outputs:
                                     q
                                  )
;

  parameter lpm_file = "UNUSED";


  output  [ 31: 0] q;
  input   [ 31: 0] data;
  input   [  4: 0] rdaddress;
  input            rdclken;
  input            rdclock;
  input   [  4: 0] wraddress;
  input            wrclock;
  input            wren;

  wire    [ 31: 0] q;
  wire    [ 31: 0] ram_q;
  wire             wrclken;
  assign wrclken = 1'b1;
  assign q = ram_q;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  altsyncram the_altsyncram
    (
      .address_a (wraddress),
      .address_b (rdaddress),
      .clock0 (wrclock),
      .clock1 (rdclock),
      .clocken0 (wrclken),
      .clocken1 (rdclken),
      .data_a (data),
      .q_b (ram_q),
      .wren_a (wren)
    );

  defparam the_altsyncram.address_reg_b = "CLOCK1",
           the_altsyncram.init_file = lpm_file,
           the_altsyncram.maximum_depth = 0,
           the_altsyncram.numwords_a = 32,
           the_altsyncram.numwords_b = 32,
           the_altsyncram.operation_mode = "DUAL_PORT",
           the_altsyncram.outdata_reg_b = "UNREGISTERED",
           the_altsyncram.ram_block_type = "AUTO",
           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
           the_altsyncram.width_a = 32,
           the_altsyncram.width_b = 32,
           the_altsyncram.widthad_a = 5,
           the_altsyncram.widthad_b = 5;


//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  altsyncram the_altsyncram
//    (
//      .address_a (wraddress),
//      .address_b (rdaddress),
//      .clock0 (wrclock),
//      .clock1 (rdclock),
//      .clocken0 (wrclken),
//      .clocken1 (rdclken),
//      .data_a (data),
//      .q_b (ram_q),
//      .wren_a (wren)
//    );
//
//  defparam the_altsyncram.address_reg_b = "CLOCK1",
//           the_altsyncram.init_file = lpm_file,
//           the_altsyncram.maximum_depth = 0,
//           the_altsyncram.numwords_a = 32,
//           the_altsyncram.numwords_b = 32,
//           the_altsyncram.operation_mode = "DUAL_PORT",
//           the_altsyncram.outdata_reg_b = "UNREGISTERED",
//           the_altsyncram.ram_block_type = "AUTO",
//           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
//           the_altsyncram.width_a = 32,
//           the_altsyncram.width_b = 32,
//           the_altsyncram.widthad_a = 5,
//           the_altsyncram.widthad_b = 5;
//
//synthesis read_comments_as_HDL off

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_dc_tag_module (
                           // inputs:
                            data,
                            rdaddress,
                            rdclken,
                            rdclock,
                            wraddress,
                            wrclock,
                            wren,

                           // outputs:
                            q
                         )
;

  parameter lpm_file = "UNUSED";


  output  [ 18: 0] q;
  input   [ 18: 0] data;
  input   [  5: 0] rdaddress;
  input            rdclken;
  input            rdclock;
  input   [  5: 0] wraddress;
  input            wrclock;
  input            wren;

  wire    [ 18: 0] q;
  wire    [ 18: 0] ram_q;
  wire             wrclken;
  assign wrclken = 1'b1;
  assign q = ram_q;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  altsyncram the_altsyncram
    (
      .address_a (wraddress),
      .address_b (rdaddress),
      .clock0 (wrclock),
      .clock1 (rdclock),
      .clocken0 (wrclken),
      .clocken1 (rdclken),
      .data_a (data),
      .q_b (ram_q),
      .wren_a (wren)
    );

  defparam the_altsyncram.address_reg_b = "CLOCK1",
           the_altsyncram.init_file = lpm_file,
           the_altsyncram.maximum_depth = 0,
           the_altsyncram.numwords_a = 64,
           the_altsyncram.numwords_b = 64,
           the_altsyncram.operation_mode = "DUAL_PORT",
           the_altsyncram.outdata_reg_b = "UNREGISTERED",
           the_altsyncram.ram_block_type = "AUTO",
           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
           the_altsyncram.width_a = 19,
           the_altsyncram.width_b = 19,
           the_altsyncram.widthad_a = 6,
           the_altsyncram.widthad_b = 6;


//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  altsyncram the_altsyncram
//    (
//      .address_a (wraddress),
//      .address_b (rdaddress),
//      .clock0 (wrclock),
//      .clock1 (rdclock),
//      .clocken0 (wrclken),
//      .clocken1 (rdclken),
//      .data_a (data),
//      .q_b (ram_q),
//      .wren_a (wren)
//    );
//
//  defparam the_altsyncram.address_reg_b = "CLOCK1",
//           the_altsyncram.init_file = lpm_file,
//           the_altsyncram.maximum_depth = 0,
//           the_altsyncram.numwords_a = 64,
//           the_altsyncram.numwords_b = 64,
//           the_altsyncram.operation_mode = "DUAL_PORT",
//           the_altsyncram.outdata_reg_b = "UNREGISTERED",
//           the_altsyncram.ram_block_type = "AUTO",
//           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
//           the_altsyncram.width_a = 19,
//           the_altsyncram.width_b = 19,
//           the_altsyncram.widthad_a = 6,
//           the_altsyncram.widthad_b = 6;
//
//synthesis read_comments_as_HDL off

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_dc_data_module (
                            // inputs:
                             byteenable,
                             data,
                             rdaddress,
                             rdclken,
                             rdclock,
                             wraddress,
                             wrclock,
                             wren,

                            // outputs:
                             q
                          )
;

  parameter lpm_file = "UNUSED";


  output  [ 31: 0] q;
  input   [  3: 0] byteenable;
  input   [ 31: 0] data;
  input   [  8: 0] rdaddress;
  input            rdclken;
  input            rdclock;
  input   [  8: 0] wraddress;
  input            wrclock;
  input            wren;

  wire    [ 31: 0] q;
  wire    [ 31: 0] ram_q;
  wire             wrclken;
  assign wrclken = 1'b1;
  assign q = ram_q;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  altsyncram the_altsyncram
    (
      .address_a (wraddress),
      .address_b (rdaddress),
      .byteena_a (byteenable),
      .clock0 (wrclock),
      .clock1 (rdclock),
      .clocken0 (wrclken),
      .clocken1 (rdclken),
      .data_a (data),
      .q_b (ram_q),
      .wren_a (wren)
    );

  defparam the_altsyncram.address_reg_b = "CLOCK1",
           the_altsyncram.maximum_depth = 0,
           the_altsyncram.numwords_a = 512,
           the_altsyncram.numwords_b = 512,
           the_altsyncram.operation_mode = "DUAL_PORT",
           the_altsyncram.outdata_reg_b = "UNREGISTERED",
           the_altsyncram.ram_block_type = "AUTO",
           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
           the_altsyncram.width_a = 32,
           the_altsyncram.width_b = 32,
           the_altsyncram.width_byteena_a = 4,
           the_altsyncram.widthad_a = 9,
           the_altsyncram.widthad_b = 9;


//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  altsyncram the_altsyncram
//    (
//      .address_a (wraddress),
//      .address_b (rdaddress),
//      .byteena_a (byteenable),
//      .clock0 (wrclock),
//      .clock1 (rdclock),
//      .clocken0 (wrclken),
//      .clocken1 (rdclken),
//      .data_a (data),
//      .q_b (ram_q),
//      .wren_a (wren)
//    );
//
//  defparam the_altsyncram.address_reg_b = "CLOCK1",
//           the_altsyncram.maximum_depth = 0,
//           the_altsyncram.numwords_a = 512,
//           the_altsyncram.numwords_b = 512,
//           the_altsyncram.operation_mode = "DUAL_PORT",
//           the_altsyncram.outdata_reg_b = "UNREGISTERED",
//           the_altsyncram.ram_block_type = "AUTO",
//           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
//           the_altsyncram.width_a = 32,
//           the_altsyncram.width_b = 32,
//           the_altsyncram.width_byteena_a = 4,
//           the_altsyncram.widthad_a = 9,
//           the_altsyncram.widthad_b = 9;
//
//synthesis read_comments_as_HDL off

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_dc_victim_module (
                              // inputs:
                               data,
                               rdaddress,
                               rdclken,
                               rdclock,
                               wraddress,
                               wrclock,
                               wren,

                              // outputs:
                               q
                            )
;

  parameter lpm_file = "UNUSED";


  output  [ 31: 0] q;
  input   [ 31: 0] data;
  input   [  2: 0] rdaddress;
  input            rdclken;
  input            rdclock;
  input   [  2: 0] wraddress;
  input            wrclock;
  input            wren;