📄 class.ptf
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}
}
}
PORT_WIRING
{
PORT clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "serial_segment";
technology = "imported components";
}
}
SOPC_Builder_Version = "0.0";
COMPONENT_BUILDER
{
HDL_PARAMETERS
{
# generated by CBDocument.getParameterContainer
# used only by Component Editor
HDL_PARAMETER prescale
{
parameter_name = "PRESCALE";
type = "integer";
default_value = "16'b0000000000000101";
editable = "1";
tooltip = "";
}
HDL_PARAMETER holdcount
{
parameter_name = "HOLDCOUNT";
type = "integer";
default_value = "32'b00000000000000011110100001001000";
editable = "1";
tooltip = "";
}
HDL_PARAMETER idle
{
parameter_name = "IDLE";
type = "integer";
default_value = "2'b00";
editable = "1";
tooltip = "";
}
HDL_PARAMETER start
{
parameter_name = "START";
type = "integer";
default_value = "2'b01";
editable = "1";
tooltip = "";
}
HDL_PARAMETER stop
{
parameter_name = "STOP";
type = "integer";
default_value = "2'b10";
editable = "1";
tooltip = "";
}
HDL_PARAMETER hold
{
parameter_name = "HOLD";
type = "integer";
default_value = "2'b11";
editable = "1";
tooltip = "";
}
}
}
}
}
WRAPPER shift_bit
{
CLASS shift_bit
{
CB_GENERATOR
{
HDL_FILES
{
FILE
{
use_in_simulation = "1";
use_in_synthesis = "1";
type = "";
filepath = "G:/FreeDev程序库和IP/serial_sigment/hdl/serial_segment.v";
}
}
top_module_name = "shift_bit";
emit_system_h = "0";
}
MODULE_DEFAULTS global_signals
{
class = "shift_bit";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT rst_n
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT prescale
{
width = "16";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT data
{
width = "16";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT start
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT busy
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT s_clk
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT s_dat
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
PORT_WIRING
{
PORT clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "shift_bit";
technology = "imported components";
}
}
SOPC_Builder_Version = "0.0";
COMPONENT_BUILDER
{
HDL_PARAMETERS
{
# generated by CBDocument.getParameterContainer
# used only by Component Editor
HDL_PARAMETER idle
{
parameter_name = "IDLE";
type = "integer";
default_value = "5'b00001";
editable = "1";
tooltip = "";
}
HDL_PARAMETER prepare_data
{
parameter_name = "PREPARE_DATA";
type = "integer";
default_value = "5'b00010";
editable = "1";
tooltip = "";
}
HDL_PARAMETER rise_clk
{
parameter_name = "RISE_CLK";
type = "integer";
default_value = "5'b00100";
editable = "1";
tooltip = "";
}
HDL_PARAMETER fall_clk
{
parameter_name = "FALL_CLK";
type = "integer";
default_value = "5'b01000";
editable = "1";
tooltip = "";
}
HDL_PARAMETER end
{
parameter_name = "END";
type = "integer";
default_value = "5'b10000";
editable = "1";
tooltip = "";
}
}
}
}
}
}
}
}
ASSOCIATED_FILES
{
Add_Program = "the_wizard_ui";
Edit_Program = "the_wizard_ui";
Generator_Program = "cb_generator.pl";
}
}
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