vga_system.fit.rpt
来自「verilog代码读写SDRAM 不带仿真」· RPT 代码 · 共 263 行 · 第 1/5 页
RPT
263 行
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[7]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[8] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[8] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|A_mul_src2[8]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[8]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[9] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[9] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|A_mul_src2[9]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[9]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[10] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[10] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|A_mul_src2[10]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[10]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[11] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[11] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|A_mul_src2[11]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[11]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[12] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[12] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|A_mul_src2[12]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[12]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[13] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[13] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|A_mul_src2[13]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[13]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[14] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[14] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|A_mul_src2[14]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[14]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[15] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[15] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|A_mul_src2[15]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src2[15]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAB ; ;
; vga_sys:inst1|cpu:the_cpu|D_bht_data[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_b4e1:auto_generated|altsyncram_abn1:altsyncram1|q_a[0] ; PORTADATAOUT ; ;
; vga_sys:inst1|cpu:the_cpu|D_bht_data[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; vga_sys:inst1|cpu:the_cpu|cpu_bht_module:cpu_bht|altsyncram:the_altsyncram|altsyncram_b4e1:auto_generated|altsyncram_abn1:altsyncram1|q_a[1] ; PORTADATAOUT ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[0] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SA[0] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[0] ; Duplicated ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; vga_sys:inst1|sdram:the_sdram|m_addr[0]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[1] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SA[1] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[1] ; Duplicated ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; vga_sys:inst1|sdram:the_sdram|m_addr[1]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[2] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SA[2] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[2] ; Duplicated ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; vga_sys:inst1|sdram:the_sdram|m_addr[2]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[3] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SA[3] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[3] ; Duplicated ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; vga_sys:inst1|sdram:the_sdram|m_addr[3]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[4] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SA[4] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[5] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SA[5] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[6] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SA[6] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[6] ; Duplicated ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; vga_sys:inst1|sdram:the_sdram|m_addr[6]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[7] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SA[7] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[7] ; Duplicated ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; vga_sys:inst1|sdram:the_sdram|m_addr[7]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[8] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SA[8] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[8] ; Duplicated ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; vga_sys:inst1|sdram:the_sdram|m_addr[8]~_Duplicate_1 ; REGOUT ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[9] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SA[9] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[10] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SA[10] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[11] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SA[11] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_addr[12] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SA[12] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_bank[0] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SBA[0] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_bank[1] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SBA[1] ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_cmd[0] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; SWE ; DATAIN ; ;
; vga_sys:inst1|sdram:the_sdram|m_cmd[0] ; Duplicated ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; vga_sys:inst1|sdram:the_sdram|m_cmd[0]~_Duplicate⌨️ 快捷键说明
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