vga_system.fit.rpt

来自「verilog代码读写SDRAM 不带仿真」· RPT 代码 · 共 263 行 · 第 1/5 页

; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
; Node                                                                                                                        ; Action          ; Operation        ; Reason                                 ; Node Port ; Node Port Name ; Destination Node                                                                                                                                            ; Destination Port ; Destination Port Name ;
+-----------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[0]                                                                                     ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[0]                                                                                     ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|A_mul_src1[0]~_Duplicate_1                                                                                                        ; REGOUT           ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[1]                                                                                     ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[1]                                                                                     ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|A_mul_src1[1]~_Duplicate_1                                                                                                        ; REGOUT           ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[2]                                                                                     ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[2]                                                                                     ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|A_mul_src1[2]~_Duplicate_1                                                                                                        ; REGOUT           ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[3]                                                                                     ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[3]                                                                                     ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|A_mul_src1[3]~_Duplicate_1                                                                                                        ; REGOUT           ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[4]                                                                                     ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[4]                                                                                     ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|A_mul_src1[4]~_Duplicate_1                                                                                                        ; REGOUT           ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[5]                                                                                     ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[5]                                                                                     ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|A_mul_src1[5]~_Duplicate_1                                                                                                        ; REGOUT           ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[6]                                                                                     ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[6]                                                                                     ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|A_mul_src1[6]~_Duplicate_1                                                                                                        ; REGOUT           ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[7]                                                                                     ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[7]                                                                                     ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|A_mul_src1[7]~_Duplicate_1                                                                                                        ; REGOUT           ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[8]                                                                                     ; Packed Register ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA            ;                       ;
; vga_sys:inst1|cpu:the_cpu|A_mul_src1[8]                                                                                     ; Duplicated      ; Register Packing ; Timing optimization                    ; REGOUT    ;                ; vga_sys:inst1|cpu:the_cpu|A_mul_src1[8]~_Duplicate_1                                                                                                        ; REGOUT           ;                       ;