vga_system.fit.rpt

来自「verilog代码读写SDRAM 不带仿真」· RPT 代码 · 共 263 行 · 第 1/5 页

and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Fitter Summary                                                                     ;
+------------------------------------+-----------------------------------------------+
; Fitter Status                      ; Successful - Sat Mar 01 10:41:14 2008         ;
; Quartus II Version                 ; 7.2 Build 203 02/05/2008 SP 2 SJ Full Version ;
; Revision Name                      ; vga_system                                    ;
; Top-level Entity Name              ; vga_system                                    ;
; Family                             ; Cyclone II                                    ;
; Device                             ; EP2C35F484C8                                  ;
; Timing Models                      ; Final                                         ;
; Total logic elements               ; 5,135 / 33,216 ( 15 % )                       ;
;     Total combinational functions  ; 4,635 / 33,216 ( 14 % )                       ;
;     Dedicated logic registers      ; 2,917 / 33,216 ( 9 % )                        ;
; Total registers                    ; 3067                                          ;
; Total pins                         ; 129 / 322 ( 40 % )                            ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 90,048 / 483,840 ( 19 % )                     ;
; Embedded Multiplier 9-bit elements ; 4 / 70 ( 6 % )                                ;
; Total PLLs                         ; 1 / 4 ( 25 % )                                ;
+------------------------------------+-----------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; EP2C35F484C8                   ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;