vga_system.fit.rpt

来自「verilog代码读写SDRAM 不带仿真」· RPT 代码 · 共 263 行 · 第 1/5 页

Fitter report for vga_system
Sat Mar 01 10:41:15 2008
Quartus II Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Netlist Optimizations
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Input Pins
  8. Output Pins
  9. Bidir Pins
 10. I/O Bank Usage
 11. All Package Pins
 12. PLL Summary
 13. PLL Usage
 14. Output Pin Default Load For Reported TCO
 15. Fitter Resource Utilization by Entity
 16. Delay Chain Summary
 17. Pad To Core Delay Chain Fanout
 18. Control Signals
 19. Global & Other Fast Signals
 20. Non-Global High Fan-Out Signals
 21. Fitter RAM Summary
 22. Fitter DSP Block Usage Summary
 23. DSP Block Details
 24. Interconnect Usage Summary
 25. LAB Logic Elements
 26. LAB-wide Signals
 27. LAB Signals Sourced
 28. LAB Signals Sourced Out
 29. LAB Distinct Inputs
 30. Fitter Device Options
 31. Operating Settings and Conditions
 32. Advanced Data - General
 33. Advanced Data - Placement Preparation
 34. Advanced Data - Placement
 35. Advanced Data - Routing
 36. Fitter Messages
 37. Fitter Suppressed Messages



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; Legal Notice ;
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Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions