read_memoryline.v

verilog代码读写SDRAM 不带仿真

//---------------------------------------------------------------
//模块名称：read_memoryline
//功能说明：读取VGA显示行
//	    
//日    期：20070917
//备    注：
//	   读取一行数据，触发条件是line变化。
//
//公司：杭州自由电子科技
//电话：[phone]
//网址：www.freefpga.com
//邮件：[e-mail]
//----------------------------------------------------------------

module read_memoryline( 
	clk,
	rst_n,
	
	// 读参数
	base_addr,
	line,
	error,
		
	// avalon主端口
	m_waitrequest,
	m_address,
	m_read,
	m_readdata,
	m_write,
	m_writedata,
	m_byteenable,
	m_burstcount,
	m_readdatavalid,
	
	// FIFO
	fifo_wrreq,
	fifo_writedata,
	fifo_wrfull,
	fifo_wrempty,
	fifo_wrusedw
	);
	
	input clk;
	input rst_n;
	
	input [31:0]base_addr;
	input [9:0]line;
	output error ;
	
	//master 接口信号
	input m_waitrequest;		// 等待
	output [31:0]m_address;		// master 地址
	output m_read;			// 读信号
	input [31:0]m_readdata;		// 读数据
	output m_write;			// 写信号
	output [31:0]m_writedata;	// 写数据
	output [3:0]m_byteenable;	// 字节选择
	output [7:0]m_burstcount;	// 突发传输数
	input  m_readdatavalid;		// 突发传输读数据有效
	
	// fifo 接口
	output fifo_wrreq;		// fifo写请求
	output fifo_writedata;		// fifo写数据
	input fifo_wrfull;		// fifo满标志
	input fifo_wrempty;		// fifo空标志
	input [8:0]fifo_wrusedw;	// fifo使用计数

	reg [31:0]m_address;
	reg m_read;
	reg [3:0]m_byteenable;
	reg [7:0]m_burstcount;
	
	reg error;			// 处理错误
	
	parameter [3:0] 
		IDLE   		= 6'b0001,	// 空闲		0x01
		R_START0 	= 6'b0010,	// 读地址准备0 	0x02
		R_START1 	= 6'b0100,	// 等待wait无效 0x04
		R_DATA		= 6'b1000;	// 读数据0	0x08
		
	reg [3:0] current_state;	

	reg [31:0] readdata;		// 读数据	
	reg [31:0] transfer_count;	// 传输计数
	reg [31:0] remain_count;	// 剩余传输
	reg [7:0]  burstcount; 		// 突发传输次数
	reg [31:0]  count;		// 一次突发传输内计数
	
	reg [9:0] old_line;
	wire start= ( old_line == line ) ? 0 : 1;	// 读启动信号

	// Avalon Master读控制状态机
	always @(posedge clk or negedge rst_n)
	if(!rst_n)
	begin
		current_state <= #1 IDLE;
		
		m_address 	<= #1 32'hzzzzzzzz;
		m_read    	<= #1 1'b0;
		m_byteenable	<= #1 4'h0;
		m_burstcount	<= #1 8'h00;
		transfer_count 	<= #1 32'h00000000;
	end
	else
	begin
		old_line <= #1 line;
		
		case(current_state)
			IDLE:	begin
					m_address 	<= #1 32'hzzzzzzzz;
					m_read    	<= #1 1'b0;
					m_write   	<= #1 1'b0;
					m_byteenable	<= #1 4'h0;
					transfer_count	<= #1 32'h00000000;
										
					if( start )
					begin
						burstcount <= #1 (copy_count < 128) ? {copy_count[6:0]}:128; // 突发传输次数
						remain_count <= #1 copy_count;	// 剩余传输数等于待传输数 
					 	current_state <= #1 R_START0;
					 end
					else 		current_state <= #1 IDLE;
					
				end 
			R_START0:	begin	// 提交address、read、byteenable、burstcount
					
					if( transfer_count == copy_count) current_state <= #1 IDLE;
					else begin
						m_address 	<= #1 source_addr + (transfer_count*4);
						m_read    	<= #1 1'b1;
						m_byteenable	<= #1 4'hf;
						m_burstcount	<= #1 burstcount;
						count		<= #1 32'h00000000;
						remain_count	<= #1 remain_count - {{24{1'b0}},burstcount};//剩余传输数
						current_state <= #1 R_DATA;
					end
				end
			R_START1:	begin
					if( m_waitrequest == 1'b1) current_state <= #1 R_START1;
					else begin
						m_read		<= #1 1'b0;
						
						current_state <= #1 R_DATA;
					end
				end
			R_DATA:	begin
					if( m_readdatavalid == 1'b0 ) 		// 数据无效等待 
						current_state <= #1 R_DATA;
					else begin
						// m_readdata数据进FIFO	
						readdata <= #1 m_readdata;
						
						count <= count + 1;		
						if( count == (burstcount-1))		//本次突发读传输完成
						begin
							m_read		<= #1 1'b0;
							m_byteenable	<= #1 4'h0;
							
							if( remain_count == 32'h00000000) 
							begin
								current_state <= IDLE;
							end
							else begin
								transfer_count	<= #1 transfer_count+ burstcount;
								burstcount 	<= #1 (remain_count < 128) ? {remain_count[6:0]}:128; // 下一次突发传输次数
								
								current_state  	<= #1 R_START0;	// 再一次启动读和写
							end
						end
						else 
							current_state <= #1 R_DATA;	//突发传输未完成，继续
					end
				end
			default:	current_state <= #1 IDLE;
			
			endcase
	end
	
	// FIFO 读写处理
	fifo_wrreq = ((current_state == R_DATA) && m_readdatavalid == 1'b0 )? 1 : 0;	//FIFO 写请求	
	fifo_writedata = m_readdata;
	
endmodule