freedev_cycloneii_50.tan.qmsg

来自「verilog代码读写SDRAM 不带仿真」· QMSG 代码 · 共 9 行 · 第 1/5 页

{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.901 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.901 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cyclon