mux_0kb.tdf

verilog代码读写SDRAM 不带仿真

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=2 LPM_WIDTH=16 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ  VERSION_END


--  Copyright (C) 1988-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 16 
SUBDESIGN mux_0kb
( 
	data[31..0]	:	input;
	result[15..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[15..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data290w[1..0]	: WIRE;
	w_data304w[1..0]	: WIRE;
	w_data316w[1..0]	: WIRE;
	w_data328w[1..0]	: WIRE;
	w_data340w[1..0]	: WIRE;
	w_data352w[1..0]	: WIRE;
	w_data364w[1..0]	: WIRE;
	w_data376w[1..0]	: WIRE;
	w_data388w[1..0]	: WIRE;
	w_data400w[1..0]	: WIRE;
	w_data412w[1..0]	: WIRE;
	w_data424w[1..0]	: WIRE;
	w_data436w[1..0]	: WIRE;
	w_data448w[1..0]	: WIRE;
	w_data460w[1..0]	: WIRE;
	w_data472w[1..0]	: WIRE;
	w_result291w	: WIRE;
	w_result297w	: WIRE;
	w_result305w	: WIRE;
	w_result311w	: WIRE;
	w_result317w	: WIRE;
	w_result323w	: WIRE;
	w_result329w	: WIRE;
	w_result335w	: WIRE;
	w_result341w	: WIRE;
	w_result347w	: WIRE;
	w_result353w	: WIRE;
	w_result359w	: WIRE;
	w_result365w	: WIRE;
	w_result371w	: WIRE;
	w_result377w	: WIRE;
	w_result383w	: WIRE;
	w_result389w	: WIRE;
	w_result395w	: WIRE;
	w_result401w	: WIRE;
	w_result407w	: WIRE;
	w_result413w	: WIRE;
	w_result419w	: WIRE;
	w_result425w	: WIRE;
	w_result431w	: WIRE;
	w_result437w	: WIRE;
	w_result443w	: WIRE;
	w_result449w	: WIRE;
	w_result455w	: WIRE;
	w_result461w	: WIRE;
	w_result467w	: WIRE;
	w_result473w	: WIRE;
	w_result479w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result473w, w_result461w, w_result449w, w_result437w, w_result425w, w_result413w, w_result401w, w_result389w, w_result377w, w_result365w, w_result353w, w_result341w, w_result329w, w_result317w, w_result305w, w_result291w);
	sel_node[] = ( sel[0..0]);
	w_data290w[] = ( data[16..16], data[0..0]);
	w_data304w[] = ( data[17..17], data[1..1]);
	w_data316w[] = ( data[18..18], data[2..2]);
	w_data328w[] = ( data[19..19], data[3..3]);
	w_data340w[] = ( data[20..20], data[4..4]);
	w_data352w[] = ( data[21..21], data[5..5]);
	w_data364w[] = ( data[22..22], data[6..6]);
	w_data376w[] = ( data[23..23], data[7..7]);
	w_data388w[] = ( data[24..24], data[8..8]);
	w_data400w[] = ( data[25..25], data[9..9]);
	w_data412w[] = ( data[26..26], data[10..10]);
	w_data424w[] = ( data[27..27], data[11..11]);
	w_data436w[] = ( data[28..28], data[12..12]);
	w_data448w[] = ( data[29..29], data[13..13]);
	w_data460w[] = ( data[30..30], data[14..14]);
	w_data472w[] = ( data[31..31], data[15..15]);
	w_result291w = w_result297w;
	w_result297w = ((sel_node[] & w_data290w[1..1]) # ((! sel_node[]) & w_data290w[0..0]));
	w_result305w = w_result311w;
	w_result311w = ((sel_node[] & w_data304w[1..1]) # ((! sel_node[]) & w_data304w[0..0]));
	w_result317w = w_result323w;
	w_result323w = ((sel_node[] & w_data316w[1..1]) # ((! sel_node[]) & w_data316w[0..0]));
	w_result329w = w_result335w;
	w_result335w = ((sel_node[] & w_data328w[1..1]) # ((! sel_node[]) & w_data328w[0..0]));
	w_result341w = w_result347w;
	w_result347w = ((sel_node[] & w_data340w[1..1]) # ((! sel_node[]) & w_data340w[0..0]));
	w_result353w = w_result359w;
	w_result359w = ((sel_node[] & w_data352w[1..1]) # ((! sel_node[]) & w_data352w[0..0]));
	w_result365w = w_result371w;
	w_result371w = ((sel_node[] & w_data364w[1..1]) # ((! sel_node[]) & w_data364w[0..0]));
	w_result377w = w_result383w;
	w_result383w = ((sel_node[] & w_data376w[1..1]) # ((! sel_node[]) & w_data376w[0..0]));
	w_result389w = w_result395w;
	w_result395w = ((sel_node[] & w_data388w[1..1]) # ((! sel_node[]) & w_data388w[0..0]));
	w_result401w = w_result407w;
	w_result407w = ((sel_node[] & w_data400w[1..1]) # ((! sel_node[]) & w_data400w[0..0]));
	w_result413w = w_result419w;
	w_result419w = ((sel_node[] & w_data412w[1..1]) # ((! sel_node[]) & w_data412w[0..0]));
	w_result425w = w_result431w;
	w_result431w = ((sel_node[] & w_data424w[1..1]) # ((! sel_node[]) & w_data424w[0..0]));
	w_result437w = w_result443w;
	w_result443w = ((sel_node[] & w_data436w[1..1]) # ((! sel_node[]) & w_data436w[0..0]));
	w_result449w = w_result455w;
	w_result455w = ((sel_node[] & w_data448w[1..1]) # ((! sel_node[]) & w_data448w[0..0]));
	w_result461w = w_result467w;
	w_result467w = ((sel_node[] & w_data460w[1..1]) # ((! sel_node[]) & w_data460w[0..0]));
	w_result473w = w_result479w;
	w_result479w = ((sel_node[] & w_data472w[1..1]) # ((! sel_node[]) & w_data472w[0..0]));
END;
--VALID FILE