freedev_cycloneii_50.map.summary

来自「verilog代码读写SDRAM 不带仿真」· SUMMARY 代码 · 共 16 行

Flow Status : Successful - Fri Aug 11 17:53:33 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : freedev_cycloneII_50
Top-level Entity Name : freedev_cycloneII_50_top
Family : Cyclone II
Device : EP2C35F484C8
Timing Models : Preliminary
Met timing requirements : N/A
Total combinational functions : 1380
Total registers : 768
Total pins : 56
Total virtual pins : 0
Total memory bits : 169,984
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0