freedev_cycloneii_50.tan.summary

来自「verilog代码读写SDRAM 不带仿真」· SUMMARY 代码 · 共 77 行

SUMMARY
77
字号
--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.367 ns
From           : D[10]
To             : freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[10]
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.627 ns
From           : freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[0]
To             : D[0]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.901 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.801 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 48.29 MHz ( period = 20.710 ns )
From           : freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21]
To             : freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ram_block1a5~porta_we_reg
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 124.22 MHz ( period = 8.050 ns )
From           : sld_hub:sld_hub_inst|jtag_debug_mode_usr1
To             : freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------

⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?