clock.v

来自「时钟发生器」· Verilog 代码 · 共 40 行

module	clock (
			clk,
			rst,
			out,
			sel
		);
input clk,rst;
output [7:0] out;
output [2:0] sel;

wire carry_sec,carry_min,carry_hour;
wire [3:0] out_to_decoder;
wire [7:0] out_sec,out_min,out_hour;

counter60	counter60_1 ( //sec
				clk,
				rst,
				carry_sec,
				out_sec);
counter60	counter60_2 ( //min
				carry_sec,
				rst,
				carry_min,
				out_min);
counter24	counter24_1 ( //hour
				carry_min,
				rst,
				out_hour);
chooser		chooser1( 
				clk,
				rst,
				out_sec,
				out_min,
				out_hour,
				out_to_decoder,
				sel);
decoder	decoder1 (
			out_to_decoder,
			out);
endmodule