counter24.v

来自「时钟发生器」· Verilog 代码 · 共 26 行

module	counter24 (
			clk,
			rst,
			out);
input	clk,rst;
output	[7:0] out;

reg	[7:0]	out;

always @ (posedge clk or negedge rst)
 begin
	if(!rst)
	  out<=8'b0;
	else begin
		if(out==8'b0010_0011)
			out<=8'b0;
		else if (out[3:0]==4'b1001)
			begin 
				out[7:4]=out[7:4]+1;
				out[3:0]<=0;
			end
		else out[3:0]<=out[3:0]+1;
	end
end
endmodule