clock.tan.qmsg

时钟发生器

{ "Info" "ITDB_TSU_RESULT" "chooser:chooser1\|out\[0\] rst clk 7.314 ns register " "Info: tsu for register \"chooser:chooser1\|out\[0\]\" (data pin = \"rst\", clock pin = \"clk\") is 7.314 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.015 ns + Longest pin register " "Info: + Longest pin to register delay is 10.015 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_73 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_73; Fanout = 35; PIN Node = 'rst'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "" { rst } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.679 ns) + CELL(0.867 ns) 10.015 ns chooser:chooser1\|out\[0\] 2 REG LC_X8_Y8_N5 5 " "Info: 2: + IC(7.679 ns) + CELL(0.867 ns) = 10.015 ns; Loc. = LC_X8_Y8_N5; Fanout = 5; REG Node = 'chooser:chooser1\|out\[0\]'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "8.546 ns" { rst chooser:chooser1|out[0] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 23.33 % " "Info: Total cell delay = 2.336 ns ( 23.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.679 ns 76.67 % " "Info: Total interconnect delay = 7.679 ns ( 76.67 % )" {  } {  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "10.015 ns" { rst chooser:chooser1|out[0] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "10.015 ns" { rst rst~out0 chooser:chooser1|out[0] } { 0.000ns 0.000ns 7.679ns } { 0.000ns 1.469ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.738 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 18; CLK Node = 'clk'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.711 ns) 2.738 ns chooser:chooser1\|out\[0\] 2 REG LC_X8_Y8_N5 5 " "Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y8_N5; Fanout = 5; REG Node = 'chooser:chooser1\|out\[0\]'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "1.269 ns" { clk chooser:chooser1|out[0] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.62 % " "Info: Total cell delay = 2.180 ns ( 79.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns 20.38 % " "Info: Total interconnect delay = 0.558 ns ( 20.38 % )" {  } {  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "2.738 ns" { clk chooser:chooser1|out[0] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 chooser:chooser1|out[0] } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "10.015 ns" { rst chooser:chooser1|out[0] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "10.015 ns" { rst rst~out0 chooser:chooser1|out[0] } { 0.000ns 0.000ns 7.679ns } { 0.000ns 1.469ns 0.867ns } } } { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "2.738 ns" { clk chooser:chooser1|out[0] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 chooser:chooser1|out[0] } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk out\[4\] chooser:chooser1\|out\[2\] 9.188 ns register " "Info: tco from clock \"clk\" to destination pin \"out\[4\]\" through register \"chooser:chooser1\|out\[2\]\" is 9.188 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.730 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 18; CLK Node = 'clk'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns chooser:chooser1\|out\[2\] 2 REG LC_X9_Y5_N6 6 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X9_Y5_N6; Fanout = 6; REG Node = 'chooser:chooser1\|out\[2\]'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "1.261 ns" { clk chooser:chooser1|out[2] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "2.730 ns" { clk chooser:chooser1|out[2] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 chooser:chooser1|out[2] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.234 ns + Longest register pin " "Info: + Longest register to pin delay is 6.234 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns chooser:chooser1\|out\[2\] 1 REG LC_X9_Y5_N6 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y5_N6; Fanout = 6; REG Node = 'chooser:chooser1\|out\[2\]'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "" { chooser:chooser1|out[2] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.364 ns) + CELL(0.590 ns) 1.954 ns decoder:decoder1\|out~57 2 COMB LC_X8_Y9_N2 2 " "Info: 2: + IC(1.364 ns) + CELL(0.590 ns) = 1.954 ns; Loc. = LC_X8_Y9_N2; Fanout = 2; COMB Node = 'decoder:decoder1\|out~57'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "1.954 ns" { chooser:chooser1|out[2] decoder:decoder1|out~57 } "NODE_NAME" } "" } } { "decoder.v" "" { Text "E:/clock/decoder.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.156 ns) + CELL(2.124 ns) 6.234 ns out\[4\] 3 PIN PIN_5 0 " "Info: 3: + IC(2.156 ns) + CELL(2.124 ns) = 6.234 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'out\[4\]'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "4.280 ns" { decoder:decoder1|out~57 out[4] } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.714 ns 43.54 % " "Info: Total cell delay = 2.714 ns ( 43.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.520 ns 56.46 % " "Info: Total interconnect delay = 3.520 ns ( 56.46 % )" {  } {  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "6.234 ns" { chooser:chooser1|out[2] decoder:decoder1|out~57 out[4] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "6.234 ns" { chooser:chooser1|out[2] decoder:decoder1|out~57 out[4] } { 0.000ns 1.364ns 2.156ns } { 0.000ns 0.590ns 2.124ns } } }  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "2.730 ns" { clk chooser:chooser1|out[2] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 chooser:chooser1|out[2] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "6.234 ns" { chooser:chooser1|out[2] decoder:decoder1|out~57 out[4] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "6.234 ns" { chooser:chooser1|out[2] decoder:decoder1|out~57 out[4] } { 0.000ns 1.364ns 2.156ns } { 0.000ns 0.590ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "chooser:chooser1\|sel\[1\] rst clk -6.506 ns register " "Info: th for register \"chooser:chooser1\|sel\[1\]\" (data pin = \"rst\", clock pin = \"clk\") is -6.506 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.730 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 18; CLK Node = 'clk'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns chooser:chooser1\|sel\[1\] 2 REG LC_X7_Y4_N2 1 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X7_Y4_N2; Fanout = 1; REG Node = 'chooser:chooser1\|sel\[1\]'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "1.261 ns" { clk chooser:chooser1|sel[1] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "2.730 ns" { clk chooser:chooser1|sel[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 chooser:chooser1|sel[1] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "chooser.v" "" { Text "E:/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.251 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.251 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_73 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_73; Fanout = 35; PIN Node = 'rst'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "" { rst } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.915 ns) + CELL(0.867 ns) 9.251 ns chooser:chooser1\|sel\[1\] 2 REG LC_X7_Y4_N2 1 " "Info: 2: + IC(6.915 ns) + CELL(0.867 ns) = 9.251 ns; Loc. = LC_X7_Y4_N2; Fanout = 1; REG Node = 'chooser:chooser1\|sel\[1\]'" {  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "7.782 ns" { rst chooser:chooser1|sel[1] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 25.25 % " "Info: Total cell delay = 2.336 ns ( 25.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.915 ns 74.75 % " "Info: Total interconnect delay = 6.915 ns ( 74.75 % )" {  } {  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "9.251 ns" { rst chooser:chooser1|sel[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "9.251 ns" { rst rst~out0 chooser:chooser1|sel[1] } { 0.000ns 0.000ns 6.915ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}  } { { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "2.730 ns" { clk chooser:chooser1|sel[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 chooser:chooser1|sel[1] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/db/clock.quartus_db" { Floorplan "E:/clock/" "" "9.251 ns" { rst chooser:chooser1|sel[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "9.251 ns" { rst rst~out0 chooser:chooser1|sel[1] } { 0.000ns 0.000ns 6.915ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 27 22:10:56 2006 " "Info: Processing ended: Fri Oct 27 22:10:56 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}