chooser.v

来自「时钟发生器」· Verilog 代码 · 共 31 行

module	chooser( clk,rst,sec,min,hour,out,sel);

input clk,rst;
input [7:0] sec,min,hour;
output [3:0] out;
output [2:0] sel;

reg [2:0] i;
reg [2:0] sel;
reg [3:0] out;

always @ (posedge clk or negedge rst)
 begin
	if(!rst) i<=0;
	else begin
		if(i==5) 	i<=0;
		else  		i<=i+1;
		case(i)
		3'd0: begin sel<=3'b000; out<=hour[7:4]; end
		3'd1: begin sel<=3'b001; out<=hour[3:0]; end
		3'd2: begin sel<=3'b010; out<=min[7:4]; end
		3'd3: begin sel<=3'b011; out<=min[3:0];end
		3'd4: begin sel<=3'b100; out<=sec[7:4];end
		3'd5: begin sel<=3'b101; out<=sec[3:0];end
		default:begin sel<=3'b111;out<=8;end
		endcase
	end
end
endmodule