clock.tan.rpt

时钟发生器

+-------------------------------------------------------------------------------------+
; th                                                                                  ;
+---------------+-------------+-----------+------+-------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                      ; To Clock ;
+---------------+-------------+-----------+------+-------------------------+----------+
; N/A           ; None        ; -6.506 ns ; rst  ; chooser:chooser1|sel[1] ; clk      ;
; N/A           ; None        ; -6.819 ns ; rst  ; chooser:chooser1|sel[2] ; clk      ;
; N/A           ; None        ; -6.942 ns ; rst  ; chooser:chooser1|out[2] ; clk      ;
; N/A           ; None        ; -6.942 ns ; rst  ; chooser:chooser1|out[1] ; clk      ;
; N/A           ; None        ; -6.942 ns ; rst  ; chooser:chooser1|sel[0] ; clk      ;
; N/A           ; None        ; -6.994 ns ; rst  ; chooser:chooser1|out[3] ; clk      ;
; N/A           ; None        ; -7.262 ns ; rst  ; chooser:chooser1|out[0] ; clk      ;
+---------------+-------------+-----------+------+-------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Oct 27 22:10:56 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "counter60:counter60_2|carry" as buffer
    Info: Detected ripple clock "counter60:counter60_1|carry" as buffer
Info: Clock "clk" has Internal fmax of 74.07 MHz between source register "counter24:counter24_1|out[1]" and destination register "chooser:chooser1|out[1]" (period= 13.5 ns)
    Info: + Longest register to register delay is 3.924 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y8_N2; Fanout = 6; REG Node = 'counter24:counter24_1|out[1]'
        Info: 2: + IC(1.258 ns) + CELL(0.442 ns) = 1.700 ns; Loc. = LC_X9_Y5_N8; Fanout = 1; COMB Node = 'chooser:chooser1|Select~741'
        Info: 3: + IC(0.714 ns) + CELL(0.590 ns) = 3.004 ns; Loc. = LC_X9_Y5_N2; Fanout = 1; COMB Node = 'chooser:chooser1|Select~742'
        Info: 4: + IC(0.442 ns) + CELL(0.478 ns) = 3.924 ns; Loc. = LC_X9_Y5_N4; Fanout = 6; REG Node = 'chooser:chooser1|out[1]'
        Info: Total cell delay = 1.510 ns ( 38.48 % )
        Info: Total interconnect delay = 2.414 ns ( 61.52 % )
    Info: - Smallest clock skew is -9.315 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.730 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 18; CLK Node = 'clk'
            Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X9_Y5_N4; Fanout = 6; REG Node = 'chooser:chooser1|out[1]'
            Info: Total cell delay = 2.180 ns ( 79.85 % )
            Info: Total interconnect delay = 0.550 ns ( 20.15 % )
        Info: - Longest clock path from clock "clk" to source register is 12.045 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 18; CLK Node = 'clk'
            Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X8_Y4_N2; Fanout = 10; REG Node = 'counter60:counter60_1|carry'
            Info: 3: + IC(3.989 ns) + CELL(0.935 ns) = 7.878 ns; Loc. = LC_X8_Y6_N2; Fanout = 9; REG Node = 'counter60:counter60_2|carry'
            Info: 4: + IC(3.456 ns) + CELL(0.711 ns) = 12.045 ns; Loc. = LC_X8_Y8_N2; Fanout = 6; REG Node = 'counter24:counter24_1|out[1]'
            Info: Total cell delay = 4.050 ns ( 33.62 % )
            Info: Total interconnect delay = 7.995 ns ( 66.38 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "chooser:chooser1|out[0]" (data pin = "rst", clock pin = "clk") is 7.314 ns
    Info: + Longest pin to register delay is 10.015 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_73; Fanout = 35; PIN Node = 'rst'
        Info: 2: + IC(7.679 ns) + CELL(0.867 ns) = 10.015 ns; Loc. = LC_X8_Y8_N5; Fanout = 5; REG Node = 'chooser:chooser1|out[0]'
        Info: Total cell delay = 2.336 ns ( 23.33 % )
        Info: Total interconnect delay = 7.679 ns ( 76.67 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.738 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 18; CLK Node = 'clk'
        Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y8_N5; Fanout = 5; REG Node = 'chooser:chooser1|out[0]'
        Info: Total cell delay = 2.180 ns ( 79.62 % )
        Info: Total interconnect delay = 0.558 ns ( 20.38 % )
Info: tco from clock "clk" to destination pin "out[4]" through register "chooser:chooser1|out[2]" is 9.188 ns
    Info: + Longest clock path from clock "clk" to source register is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 18; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X9_Y5_N6; Fanout = 6; REG Node = 'chooser:chooser1|out[2]'
        Info: Total cell delay = 2.180 ns ( 79.85 % )
        Info: Total interconnect delay = 0.550 ns ( 20.15 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.234 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y5_N6; Fanout = 6; REG Node = 'chooser:chooser1|out[2]'
        Info: 2: + IC(1.364 ns) + CELL(0.590 ns) = 1.954 ns; Loc. = LC_X8_Y9_N2; Fanout = 2; COMB Node = 'decoder:decoder1|out~57'
        Info: 3: + IC(2.156 ns) + CELL(2.124 ns) = 6.234 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'out[4]'
        Info: Total cell delay = 2.714 ns ( 43.54 % )
        Info: Total interconnect delay = 3.520 ns ( 56.46 % )
Info: th for register "chooser:chooser1|sel[1]" (data pin = "rst", clock pin = "clk") is -6.506 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 18; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X7_Y4_N2; Fanout = 1; REG Node = 'chooser:chooser1|sel[1]'
        Info: Total cell delay = 2.180 ns ( 79.85 % )
        Info: Total interconnect delay = 0.550 ns ( 20.15 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 9.