📄 clock.fit.rpt
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+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.57) ; Number of LABs (Total = 14) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 6 ;
; 1 Clock ; 7 ;
; 1 Clock enable ; 5 ;
; 2 Clocks ; 4 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 5.64) ; Number of LABs (Total = 14) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 4 ;
; 2 ; 2 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 11 ; 2 ;
; 12 ; 2 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 4.21) ; Number of LABs (Total = 14) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 4 ;
; 2 ; 2 ;
; 3 ; 0 ;
; 4 ; 3 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 2 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 7.36) ; Number of LABs (Total = 14) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 2 ;
; 4 ; 4 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 2 ;
; 13 ; 0 ;
; 14 ; 1 ;
; 15 ; 0 ;
; 16 ; 1 ;
; 17 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Fri Oct 27 22:10:48 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off clock -c clock
Info: Selected device EP1C3T144C8 for design "clock"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EP1C6T144C8 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Automatically promoted signal "clk" to use Global clock in PIN 16
Info: Automatically promoted some destinations of signal "counter60:counter60_1|carry" to use Global clock
Info: Destination "counter60:counter60_1|carry" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "counter60:counter60_2|carry" to use Global clock
Info: Destination "counter60:counter60_2|carry" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "rst" to use Global clock
Info: Destination "chooser:chooser1|sel[2]" may be non-global or may not use global clock
Info: Destination "chooser:chooser1|sel[1]" may be non-global or may not use global clock
Info: Destination "chooser:chooser1|sel[0]" may be non-global or may not use global clock
Info: Destination "chooser:chooser1|out[3]" may be non-global or may not use global clock
Info: Destination "chooser:chooser1|out[2]" may be non-global or may not use global clock
Info: Destination "chooser:chooser1|out[1]" may be non-global or may not use global clock
Info: Destination "chooser:chooser1|out[0]" may be non-global or may not use global clock
Info: Pin "rst" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 3.244 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y8; Fanout = 5; REG Node = 'counter24:counter24_1|out[2]'
Info: 2: + IC(0.578 ns) + CELL(0.442 ns) = 1.020 ns; Loc. = LAB_X9_Y8; Fanout = 1; COMB Node = 'chooser:chooser1|Select~737'
Info: 3: + IC(1.119 ns) + CELL(0.292 ns) = 2.431 ns; Loc. = LAB_X9_Y5; Fanout = 1; COMB Node = 'chooser:chooser1|Select~738'
Info: 4: + IC(0.075 ns) + CELL(0.738 ns) = 3.244 ns; Loc. = LAB_X9_Y5; Fanout = 6; REG Node = 'chooser:chooser1|out[2]'
Info: Total cell delay = 1.472 ns ( 45.38 % )
Info: Total interconnect delay = 1.772 ns ( 54.62 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%.
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin out[0] has GND driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Processing ended: Fri Oct 27 22:10:52 2006
Info: Elapsed time: 00:00:04
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