clock.tan.qmsg

时钟发生器

{ "Info" "ITDB_TH_RESULT" "chooser:chooser1\|sel\[2\] rst clk -0.716 ns register " "Info: th for register \"chooser:chooser1\|sel\[2\]\" (data pin = \"rst\", clock pin = \"clk\") is -0.716 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.767 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'clk'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns chooser:chooser1\|sel\[2\] 2 REG LC_X9_Y9_N2 1 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X9_Y9_N2; Fanout = 1; REG Node = 'chooser:chooser1\|sel\[2\]'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "1.298 ns" { clk chooser:chooser1|sel[2] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 78.79 % " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns 21.21 % " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "2.767 ns" { clk chooser:chooser1|sel[2] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { clk clk~out0 chooser:chooser1|sel[2] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.498 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_16 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 35; PIN Node = 'rst'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { rst } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.162 ns) + CELL(0.867 ns) 3.498 ns chooser:chooser1\|sel\[2\] 2 REG LC_X9_Y9_N2 1 " "Info: 2: + IC(1.162 ns) + CELL(0.867 ns) = 3.498 ns; Loc. = LC_X9_Y9_N2; Fanout = 1; REG Node = 'chooser:chooser1\|sel\[2\]'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "2.029 ns" { rst chooser:chooser1|sel[2] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 66.78 % " "Info: Total cell delay = 2.336 ns ( 66.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns 33.22 % " "Info: Total interconnect delay = 1.162 ns ( 33.22 % )" {  } {  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "3.498 ns" { rst chooser:chooser1|sel[2] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "3.498 ns" { rst rst~out0 chooser:chooser1|sel[2] } { 0.000ns 0.000ns 1.162ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "2.767 ns" { clk chooser:chooser1|sel[2] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { clk clk~out0 chooser:chooser1|sel[2] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "3.498 ns" { rst chooser:chooser1|sel[2] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "3.498 ns" { rst rst~out0 chooser:chooser1|sel[2] } { 0.000ns 0.000ns 1.162ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 27 22:16:34 2006 " "Info: Processing ended: Fri Oct 27 22:16:34 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}