clock.tan.qmsg

时钟发生器

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "counter60:counter60_2\|carry " "Info: Detected ripple clock \"counter60:counter60_2\|carry\" as buffer" {  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 7 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "counter60:counter60_2\|carry" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter60:counter60_1\|carry " "Info: Detected ripple clock \"counter60:counter60_1\|carry\" as buffer" {  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 7 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "counter60:counter60_1\|carry" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter24:counter24_1\|out\[3\] register chooser:chooser1\|out\[3\] 78.29 MHz 12.773 ns Internal " "Info: Clock \"clk\" has Internal fmax of 78.29 MHz between source register \"counter24:counter24_1\|out\[3\]\" and destination register \"chooser:chooser1\|out\[3\]\" (period= 12.773 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.205 ns + Longest register register " "Info: + Longest register to register delay is 3.205 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:counter24_1\|out\[3\] 1 REG LC_X9_Y7_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y7_N6; Fanout = 4; REG Node = 'counter24:counter24_1\|out\[3\]'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { counter24:counter24_1|out[3] } "NODE_NAME" } "" } } { "counter24.v" "" { Text "E:/clock/clock/counter24.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.545 ns) + CELL(0.114 ns) 0.659 ns chooser:chooser1\|Select~734 2 COMB LC_X9_Y7_N9 1 " "Info: 2: + IC(0.545 ns) + CELL(0.114 ns) = 0.659 ns; Loc. = LC_X9_Y7_N9; Fanout = 1; COMB Node = 'chooser:chooser1\|Select~734'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "0.659 ns" { counter24:counter24_1|out[3] chooser:chooser1|Select~734 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.190 ns) + CELL(0.442 ns) 2.291 ns chooser:chooser1\|Select~735 3 COMB LC_X9_Y8_N7 1 " "Info: 3: + IC(1.190 ns) + CELL(0.442 ns) = 2.291 ns; Loc. = LC_X9_Y8_N7; Fanout = 1; COMB Node = 'chooser:chooser1\|Select~735'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "1.632 ns" { chooser:chooser1|Select~734 chooser:chooser1|Select~735 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.478 ns) 3.205 ns chooser:chooser1\|out\[3\] 4 REG LC_X9_Y8_N9 6 " "Info: 4: + IC(0.436 ns) + CELL(0.478 ns) = 3.205 ns; Loc. = LC_X9_Y8_N9; Fanout = 6; REG Node = 'chooser:chooser1\|out\[3\]'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "0.914 ns" { chooser:chooser1|Select~735 chooser:chooser1|out[3] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.034 ns 32.26 % " "Info: Total cell delay = 1.034 ns ( 32.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.171 ns 67.74 % " "Info: Total interconnect delay = 2.171 ns ( 67.74 % )" {  } {  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "3.205 ns" { counter24:counter24_1|out[3] chooser:chooser1|Select~734 chooser:chooser1|Select~735 chooser:chooser1|out[3] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "3.205 ns" { counter24:counter24_1|out[3] chooser:chooser1|Select~734 chooser:chooser1|Select~735 chooser:chooser1|out[3] } { 0.000ns 0.545ns 1.190ns 0.436ns } { 0.000ns 0.114ns 0.442ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.307 ns - Smallest " "Info: - Smallest clock skew is -9.307 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.738 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'clk'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.711 ns) 2.738 ns chooser:chooser1\|out\[3\] 2 REG LC_X9_Y8_N9 6 " "Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X9_Y8_N9; Fanout = 6; REG Node = 'chooser:chooser1\|out\[3\]'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "1.269 ns" { clk chooser:chooser1|out[3] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.62 % " "Info: Total cell delay = 2.180 ns ( 79.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns 20.38 % " "Info: Total interconnect delay = 0.558 ns ( 20.38 % )" {  } {  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "2.738 ns" { clk chooser:chooser1|out[3] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 chooser:chooser1|out[3] } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.045 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'clk'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.935 ns) 2.962 ns counter60:counter60_1\|carry 2 REG LC_X8_Y6_N2 10 " "Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N2; Fanout = 10; REG Node = 'counter60:counter60_1\|carry'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "1.493 ns" { clk counter60:counter60_1|carry } "NODE_NAME" } "" } } { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.462 ns) + CELL(0.935 ns) 7.359 ns counter60:counter60_2\|carry 3 REG LC_X8_Y8_N2 9 " "Info: 3: + IC(3.462 ns) + CELL(0.935 ns) = 7.359 ns; Loc. = LC_X8_Y8_N2; Fanout = 9; REG Node = 'counter60:counter60_2\|carry'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "4.397 ns" { counter60:counter60_1|carry counter60:counter60_2|carry } "NODE_NAME" } "" } } { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.975 ns) + CELL(0.711 ns) 12.045 ns counter24:counter24_1\|out\[3\] 4 REG LC_X9_Y7_N6 4 " "Info: 4: + IC(3.975 ns) + CELL(0.711 ns) = 12.045 ns; Loc. = LC_X9_Y7_N6; Fanout = 4; REG Node = 'counter24:counter24_1\|out\[3\]'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "4.686 ns" { counter60:counter60_2|carry counter24:counter24_1|out[3] } "NODE_NAME" } "" } } { "counter24.v" "" { Text "E:/clock/clock/counter24.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns 33.62 % " "Info: Total cell delay = 4.050 ns ( 33.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.995 ns 66.38 % " "Info: Total interconnect delay = 7.995 ns ( 66.38 % )" {  } {  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "12.045 ns" { clk counter60:counter60_1|carry counter60:counter60_2|carry counter24:counter24_1|out[3] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "12.045 ns" { clk clk~out0 counter60:counter60_1|carry counter60:counter60_2|carry counter24:counter24_1|out[3] } { 0.000ns 0.000ns 0.558ns 3.462ns 3.975ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "2.738 ns" { clk chooser:chooser1|out[3] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 chooser:chooser1|out[3] } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "12.045 ns" { clk counter60:counter60_1|carry counter60:counter60_2|carry counter24:counter24_1|out[3] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "12.045 ns" { clk clk~out0 counter60:counter60_1|carry counter60:counter60_2|carry counter24:counter24_1|out[3] } { 0.000ns 0.000ns 0.558ns 3.462ns 3.975ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "counter24.v" "" { Text "E:/clock/clock/counter24.v" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 5 -1 0 } }  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "3.205 ns" { counter24:counter24_1|out[3] chooser:chooser1|Select~734 chooser:chooser1|Select~735 chooser:chooser1|out[3] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "3.205 ns" { counter24:counter24_1|out[3] chooser:chooser1|Select~734 chooser:chooser1|Select~735 chooser:chooser1|out[3] } { 0.000ns 0.545ns 1.190ns 0.436ns } { 0.000ns 0.114ns 0.442ns 0.478ns } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "2.738 ns" { clk chooser:chooser1|out[3] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 chooser:chooser1|out[3] } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "12.045 ns" { clk counter60:counter60_1|carry counter60:counter60_2|carry counter24:counter24_1|out[3] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "12.045 ns" { clk clk~out0 counter60:counter60_1|carry counter60:counter60_2|carry counter24:counter24_1|out[3] } { 0.000ns 0.000ns 0.558ns 3.462ns 3.975ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "chooser:chooser1\|sel\[1\] rst clk 0.973 ns register " "Info: tsu for register \"chooser:chooser1\|sel\[1\]\" (data pin = \"rst\", clock pin = \"clk\") is 0.973 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.666 ns + Longest pin register " "Info: + Longest pin to register delay is 3.666 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_16 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 35; PIN Node = 'rst'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { rst } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.330 ns) + CELL(0.867 ns) 3.666 ns chooser:chooser1\|sel\[1\] 2 REG LC_X10_Y5_N2 1 " "Info: 2: + IC(1.330 ns) + CELL(0.867 ns) = 3.666 ns; Loc. = LC_X10_Y5_N2; Fanout = 1; REG Node = 'chooser:chooser1\|sel\[1\]'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "2.197 ns" { rst chooser:chooser1|sel[1] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 63.72 % " "Info: Total cell delay = 2.336 ns ( 63.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.330 ns 36.28 % " "Info: Total interconnect delay = 1.330 ns ( 36.28 % )" {  } {  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "3.666 ns" { rst chooser:chooser1|sel[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "3.666 ns" { rst rst~out0 chooser:chooser1|sel[1] } { 0.000ns 0.000ns 1.330ns } { 0.000ns 1.469ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.730 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'clk'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns chooser:chooser1\|sel\[1\] 2 REG LC_X10_Y5_N2 1 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X10_Y5_N2; Fanout = 1; REG Node = 'chooser:chooser1\|sel\[1\]'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "1.261 ns" { clk chooser:chooser1|sel[1] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "2.730 ns" { clk chooser:chooser1|sel[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 chooser:chooser1|sel[1] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "3.666 ns" { rst chooser:chooser1|sel[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "3.666 ns" { rst rst~out0 chooser:chooser1|sel[1] } { 0.000ns 0.000ns 1.330ns } { 0.000ns 1.469ns 0.867ns } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "2.730 ns" { clk chooser:chooser1|sel[1] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 chooser:chooser1|sel[1] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk out\[7\] chooser:chooser1\|out\[2\] 9.492 ns register " "Info: tco from clock \"clk\" to destination pin \"out\[7\]\" through register \"chooser:chooser1\|out\[2\]\" is 9.492 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.740 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'clk'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns chooser:chooser1\|out\[2\] 2 REG LC_X10_Y7_N9 6 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X10_Y7_N9; Fanout = 6; REG Node = 'chooser:chooser1\|out\[2\]'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "1.271 ns" { clk chooser:chooser1|out[2] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.56 % " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns 20.44 % " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "2.740 ns" { clk chooser:chooser1|out[2] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 chooser:chooser1|out[2] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.528 ns + Longest register pin " "Info: + Longest register to pin delay is 6.528 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns chooser:chooser1\|out\[2\] 1 REG LC_X10_Y7_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y7_N9; Fanout = 6; REG Node = 'chooser:chooser1\|out\[2\]'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { chooser:chooser1|out[2] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.670 ns) + CELL(0.590 ns) 2.260 ns decoder:decoder1\|out~57 2 COMB LC_X8_Y9_N5 2 " "Info: 2: + IC(1.670 ns) + CELL(0.590 ns) = 2.260 ns; Loc. = LC_X8_Y9_N5; Fanout = 2; COMB Node = 'decoder:decoder1\|out~57'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "2.260 ns" { chooser:chooser1|out[2] decoder:decoder1|out~57 } "NODE_NAME" } "" } } { "decoder.v" "" { Text "E:/clock/clock/decoder.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.160 ns) + CELL(2.108 ns) 6.528 ns out\[7\] 3 PIN PIN_140 0 " "Info: 3: + IC(2.160 ns) + CELL(2.108 ns) = 6.528 ns; Loc. = PIN_140; Fanout = 0; PIN Node = 'out\[7\]'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "4.268 ns" { decoder:decoder1|out~57 out[7] } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/clock/clock/clock.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.698 ns 41.33 % " "Info: Total cell delay = 2.698 ns ( 41.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.830 ns 58.67 % " "Info: Total interconnect delay = 3.830 ns ( 58.67 % )" {  } {  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "6.528 ns" { chooser:chooser1|out[2] decoder:decoder1|out~57 out[7] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "6.528 ns" { chooser:chooser1|out[2] decoder:decoder1|out~57 out[7] } { 0.000ns 1.670ns 2.160ns } { 0.000ns 0.590ns 2.108ns } } }  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "2.740 ns" { clk chooser:chooser1|out[2] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 chooser:chooser1|out[2] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "6.528 ns" { chooser:chooser1|out[2] decoder:decoder1|out~57 out[7] } "NODE_NAME" } "" } } { "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda_software/quartus50/bin/Technology_Viewer.qrui" "6.528 ns" { chooser:chooser1|out[2] decoder:decoder1|out~57 out[7] } { 0.000ns 1.670ns 2.160ns } { 0.000ns 0.590ns 2.108ns } } }  } 0}