clock.fit.qmsg

时钟发生器

{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "11 unused 3.30 0 11 0 " "Info: Number of I/O pins in group: 11 (unused VREF, 3.30 VCCIO, 0 input, 11 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 4 18 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  18 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 26 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.001 ns register register " "Info: Estimated most critical path is register to register delay of 3.001 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:counter24_1\|out\[3\] 1 REG LAB_X9_Y7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y7; Fanout = 4; REG Node = 'counter24:counter24_1\|out\[3\]'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { counter24:counter24_1|out[3] } "NODE_NAME" } "" } } { "counter24.v" "" { Text "E:/clock/clock/counter24.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.352 ns) + CELL(0.442 ns) 0.794 ns chooser:chooser1\|Select~734 2 COMB LAB_X9_Y7 1 " "Info: 2: + IC(0.352 ns) + CELL(0.442 ns) = 0.794 ns; Loc. = LAB_X9_Y7; Fanout = 1; COMB Node = 'chooser:chooser1\|Select~734'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "0.794 ns" { counter24:counter24_1|out[3] chooser:chooser1|Select~734 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.085 ns) + CELL(0.292 ns) 2.171 ns chooser:chooser1\|Select~735 3 COMB LAB_X9_Y8 1 " "Info: 3: + IC(1.085 ns) + CELL(0.292 ns) = 2.171 ns; Loc. = LAB_X9_Y8; Fanout = 1; COMB Node = 'chooser:chooser1\|Select~735'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "1.377 ns" { chooser:chooser1|Select~734 chooser:chooser1|Select~735 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.607 ns) 3.001 ns chooser:chooser1\|out\[3\] 4 REG LAB_X9_Y8 6 " "Info: 4: + IC(0.223 ns) + CELL(0.607 ns) = 3.001 ns; Loc. = LAB_X9_Y8; Fanout = 6; REG Node = 'chooser:chooser1\|out\[3\]'" {  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "0.830 ns" { chooser:chooser1|Select~735 chooser:chooser1|out[3] } "NODE_NAME" } "" } } { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.341 ns 44.69 % " "Info: Total cell delay = 1.341 ns ( 44.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.660 ns 55.31 % " "Info: Total interconnect delay = 1.660 ns ( 55.31 % )" {  } {  } 0}  } { { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "3.001 ns" { counter24:counter24_1|out[3] chooser:chooser1|Select~734 chooser:chooser1|Select~735 chooser:chooser1|out[3] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out\[0\] GND " "Info: Pin out\[0\] has GND driving its datain port" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 8 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out\[0\]" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { out[0] } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { out[0] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 27 22:16:31 2006 " "Info: Processing ended: Fri Oct 27 22:16:31 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}