clock.fit.qmsg

时钟发生器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 27 22:16:27 2006 " "Info: Processing started: Fri Oct 27 22:16:27 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off clock -c clock " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off clock -c clock" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "clock EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design \"clock\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "13 13 " "Info: No exact pin location assignment(s) for 13 pins of 13 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[0\] " "Info: Pin out\[0\] not assigned to an exact location on the device" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 8 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out\[0\]" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { out[0] } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { out[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[1\] " "Info: Pin out\[1\] not assigned to an exact location on the device" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 8 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out\[1\]" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { out[1] } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { out[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[2\] " "Info: Pin out\[2\] not assigned to an exact location on the device" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 8 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out\[2\]" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { out[2] } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { out[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[3\] " "Info: Pin out\[3\] not assigned to an exact location on the device" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 8 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out\[3\]" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { out[3] } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { out[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[4\] " "Info: Pin out\[4\] not assigned to an exact location on the device" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 8 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out\[4\]" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { out[4] } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { out[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[5\] " "Info: Pin out\[5\] not assigned to an exact location on the device" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 8 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out\[5\]" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { out[5] } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { out[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[6\] " "Info: Pin out\[6\] not assigned to an exact location on the device" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 8 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out\[6\]" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { out[6] } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { out[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[7\] " "Info: Pin out\[7\] not assigned to an exact location on the device" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 8 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out\[7\]" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { out[7] } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { out[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "sel\[0\] " "Info: Pin sel\[0\] not assigned to an exact location on the device" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 9 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sel\[0\]" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { sel[0] } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { sel[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "sel\[1\] " "Info: Pin sel\[1\] not assigned to an exact location on the device" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 9 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sel\[1\]" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { sel[1] } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { sel[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "sel\[2\] " "Info: Pin sel\[2\] not assigned to an exact location on the device" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 9 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sel\[2\]" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { sel[2] } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { sel[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 7 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { clk } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { clk } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rst " "Info: Pin rst not assigned to an exact location on the device" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 7 -1 0 } } { "c:/eda_software/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/eda_software/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "E:/clock/clock/db/clock_cmp.qrpt" "" { Report "E:/clock/clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/clock/clock/db/clock.quartus_db" { Floorplan "E:/clock/clock/" "" "" { rst } "NODE_NAME" } "" } } { "E:/clock/clock/clock.fld" "" { Floorplan "E:/clock/clock/clock.fld" "" "" { rst } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 17 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 17" {  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "counter60:counter60_1\|carry Global clock " "Info: Automatically promoted some destinations of signal \"counter60:counter60_1\|carry\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "counter60:counter60_1\|carry " "Info: Destination \"counter60:counter60_1\|carry\" may be non-global or may not use global clock" {  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 7 -1 0 } }  } 0}  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "counter60:counter60_2\|carry Global clock " "Info: Automatically promoted some destinations of signal \"counter60:counter60_2\|carry\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "counter60:counter60_2\|carry " "Info: Destination \"counter60:counter60_2\|carry\" may be non-global or may not use global clock" {  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 7 -1 0 } }  } 0}  } { { "counter60.v" "" { Text "E:/clock/clock/counter60.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst Global clock in PIN 16 " "Info: Automatically promoted some destinations of signal \"rst\" to use Global clock in PIN 16" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|sel\[2\] " "Info: Destination \"chooser:chooser1\|sel\[2\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|sel\[1\] " "Info: Destination \"chooser:chooser1\|sel\[1\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|sel\[0\] " "Info: Destination \"chooser:chooser1\|sel\[0\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|out\[3\] " "Info: Destination \"chooser:chooser1\|out\[3\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|out\[2\] " "Info: Destination \"chooser:chooser1\|out\[2\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|out\[1\] " "Info: Destination \"chooser:chooser1\|out\[1\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 5 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "chooser:chooser1\|out\[0\] " "Info: Destination \"chooser:chooser1\|out\[0\]\" may be non-global or may not use global clock" {  } { { "chooser.v" "" { Text "E:/clock/clock/chooser.v" 5 -1 0 } }  } 0}  } { { "clock.v" "" { Text "E:/clock/clock/clock.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}