clock.tan.rpt

时钟发生器

+-------------------------------------------------------------------------------------+
; th                                                                                  ;
+---------------+-------------+-----------+------+-------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                      ; To Clock ;
+---------------+-------------+-----------+------+-------------------------+----------+
; N/A           ; None        ; -0.716 ns ; rst  ; chooser:chooser1|sel[2] ; clk      ;
; N/A           ; None        ; -0.720 ns ; rst  ; chooser:chooser1|out[3] ; clk      ;
; N/A           ; None        ; -0.732 ns ; rst  ; chooser:chooser1|out[2] ; clk      ;
; N/A           ; None        ; -0.732 ns ; rst  ; chooser:chooser1|out[1] ; clk      ;
; N/A           ; None        ; -0.732 ns ; rst  ; chooser:chooser1|sel[0] ; clk      ;
; N/A           ; None        ; -0.766 ns ; rst  ; chooser:chooser1|out[0] ; clk      ;
; N/A           ; None        ; -0.921 ns ; rst  ; chooser:chooser1|sel[1] ; clk      ;
+---------------+-------------+-----------+------+-------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Oct 27 22:16:34 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "counter60:counter60_2|carry" as buffer
    Info: Detected ripple clock "counter60:counter60_1|carry" as buffer
Info: Clock "clk" has Internal fmax of 78.29 MHz between source register "counter24:counter24_1|out[3]" and destination register "chooser:chooser1|out[3]" (period= 12.773 ns)
    Info: + Longest register to register delay is 3.205 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y7_N6; Fanout = 4; REG Node = 'counter24:counter24_1|out[3]'
        Info: 2: + IC(0.545 ns) + CELL(0.114 ns) = 0.659 ns; Loc. = LC_X9_Y7_N9; Fanout = 1; COMB Node = 'chooser:chooser1|Select~734'
        Info: 3: + IC(1.190 ns) + CELL(0.442 ns) = 2.291 ns; Loc. = LC_X9_Y8_N7; Fanout = 1; COMB Node = 'chooser:chooser1|Select~735'
        Info: 4: + IC(0.436 ns) + CELL(0.478 ns) = 3.205 ns; Loc. = LC_X9_Y8_N9; Fanout = 6; REG Node = 'chooser:chooser1|out[3]'
        Info: Total cell delay = 1.034 ns ( 32.26 % )
        Info: Total interconnect delay = 2.171 ns ( 67.74 % )
    Info: - Smallest clock skew is -9.307 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.738 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'clk'
            Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X9_Y8_N9; Fanout = 6; REG Node = 'chooser:chooser1|out[3]'
            Info: Total cell delay = 2.180 ns ( 79.62 % )
            Info: Total interconnect delay = 0.558 ns ( 20.38 % )
        Info: - Longest clock path from clock "clk" to source register is 12.045 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'clk'
            Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N2; Fanout = 10; REG Node = 'counter60:counter60_1|carry'
            Info: 3: + IC(3.462 ns) + CELL(0.935 ns) = 7.359 ns; Loc. = LC_X8_Y8_N2; Fanout = 9; REG Node = 'counter60:counter60_2|carry'
            Info: 4: + IC(3.975 ns) + CELL(0.711 ns) = 12.045 ns; Loc. = LC_X9_Y7_N6; Fanout = 4; REG Node = 'counter24:counter24_1|out[3]'
            Info: Total cell delay = 4.050 ns ( 33.62 % )
            Info: Total interconnect delay = 7.995 ns ( 66.38 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "chooser:chooser1|sel[1]" (data pin = "rst", clock pin = "clk") is 0.973 ns
    Info: + Longest pin to register delay is 3.666 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 35; PIN Node = 'rst'
        Info: 2: + IC(1.330 ns) + CELL(0.867 ns) = 3.666 ns; Loc. = LC_X10_Y5_N2; Fanout = 1; REG Node = 'chooser:chooser1|sel[1]'
        Info: Total cell delay = 2.336 ns ( 63.72 % )
        Info: Total interconnect delay = 1.330 ns ( 36.28 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X10_Y5_N2; Fanout = 1; REG Node = 'chooser:chooser1|sel[1]'
        Info: Total cell delay = 2.180 ns ( 79.85 % )
        Info: Total interconnect delay = 0.550 ns ( 20.15 % )
Info: tco from clock "clk" to destination pin "out[7]" through register "chooser:chooser1|out[2]" is 9.492 ns
    Info: + Longest clock path from clock "clk" to source register is 2.740 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'clk'
        Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X10_Y7_N9; Fanout = 6; REG Node = 'chooser:chooser1|out[2]'
        Info: Total cell delay = 2.180 ns ( 79.56 % )
        Info: Total interconnect delay = 0.560 ns ( 20.44 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.528 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y7_N9; Fanout = 6; REG Node = 'chooser:chooser1|out[2]'
        Info: 2: + IC(1.670 ns) + CELL(0.590 ns) = 2.260 ns; Loc. = LC_X8_Y9_N5; Fanout = 2; COMB Node = 'decoder:decoder1|out~57'
        Info: 3: + IC(2.160 ns) + CELL(2.108 ns) = 6.528 ns; Loc. = PIN_140; Fanout = 0; PIN Node = 'out[7]'
        Info: Total cell delay = 2.698 ns ( 41.33 % )
        Info: Total interconnect delay = 3.830 ns ( 58.67 % )
Info: th for register "chooser:chooser1|sel[2]" (data pin = "rst", clock pin = "clk") is -0.716 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.767 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'clk'
        Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X9_Y9_N2; Fanout = 1; REG Node = 'chooser:chooser1|sel[2]'
        Info: Total cell delay = 2.180 ns ( 78.79 % )
        Info: Total interconnect delay = 0.587 ns ( 21.21 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay