clock.fit.rpt

时钟发生器

; Control Signals                                                                                                                             ;
+------------------------------------+--------------+---------+----------------------------+--------+----------------------+------------------+
; Name                               ; Location     ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ;
+------------------------------------+--------------+---------+----------------------------+--------+----------------------+------------------+
; chooser:chooser1|i[2]              ; LC_X10_Y6_N9 ; 14      ; Sync. load                 ; no     ; --                   ; --               ;
; clk                                ; PIN_17       ; 18      ; Clock                      ; yes    ; Global clock         ; GCLK3            ;
; counter60:counter60_1|add~166      ; LC_X10_Y6_N6 ; 1       ; Clock enable               ; no     ; --                   ; --               ;
; counter60:counter60_1|carry        ; LC_X8_Y6_N2  ; 10      ; Clock                      ; yes    ; Global clock         ; GCLK0            ;
; counter60:counter60_1|reduce_nor~0 ; LC_X9_Y6_N3  ; 3       ; Clock enable               ; no     ; --                   ; --               ;
; counter60:counter60_2|add~161      ; LC_X10_Y7_N7 ; 1       ; Clock enable               ; no     ; --                   ; --               ;
; counter60:counter60_2|carry        ; LC_X8_Y8_N2  ; 9       ; Clock                      ; yes    ; Global clock         ; GCLK1            ;
; counter60:counter60_2|reduce_nor~0 ; LC_X9_Y8_N6  ; 3       ; Clock enable               ; no     ; --                   ; --               ;
; rst                                ; PIN_16       ; 35      ; Async. clear, Clock enable ; yes    ; Global clock         ; GCLK2            ;
+------------------------------------+--------------+---------+----------------------------+--------+----------------------+------------------+


+-----------------------------------------------------------------------------------------------+
; Global & Other Fast Signals                                                                   ;
+-----------------------------+-------------+---------+----------------------+------------------+
; Name                        ; Location    ; Fan-Out ; Global Resource Used ; Global Line Name ;
+-----------------------------+-------------+---------+----------------------+------------------+
; clk                         ; PIN_17      ; 18      ; Global clock         ; GCLK3            ;
; counter60:counter60_1|carry ; LC_X8_Y6_N2 ; 10      ; Global clock         ; GCLK0            ;
; counter60:counter60_2|carry ; LC_X8_Y8_N2 ; 9       ; Global clock         ; GCLK1            ;
; rst                         ; PIN_16      ; 35      ; Global clock         ; GCLK2            ;
+-----------------------------+-------------+---------+----------------------+------------------+


+--------------------------------------------------+
; Non-Global High Fan-Out Signals                  ;
+----------------------------------------+---------+
; Name                                   ; Fan-Out ;
+----------------------------------------+---------+
; chooser:chooser1|i[0]                  ; 15      ;
; chooser:chooser1|i[2]                  ; 14      ;
; chooser:chooser1|i[1]                  ; 9       ;
; counter24:counter24_1|out[0]           ; 7       ;
; counter60:counter60_2|out[0]           ; 6       ;
; counter24:counter24_1|out[1]           ; 6       ;
; chooser:chooser1|out[1]                ; 6       ;
; chooser:chooser1|out[2]                ; 6       ;
; chooser:chooser1|out[3]                ; 6       ;
; counter60:counter60_2|out[1]           ; 5       ;
; counter60:counter60_1|out[1]           ; 5       ;
; counter60:counter60_2|out[2]           ; 5       ;
; counter60:counter60_1|out[2]           ; 5       ;
; counter24:counter24_1|out[2]           ; 5       ;
; chooser:chooser1|out[0]                ; 5       ;
; counter60:counter60_1|out[3]           ; 4       ;
; counter24:counter24_1|out[3]           ; 4       ;
; counter60:counter60_2|out[3]           ; 4       ;
; counter60:counter60_2|reduce_nor~0     ; 3       ;
; counter60:counter60_1|reduce_nor~0     ; 3       ;
; counter24:counter24_1|out~281          ; 3       ;
; counter60:counter60_2|out[5]           ; 3       ;
; counter24:counter24_1|out[5]           ; 3       ;
; counter60:counter60_1|out[5]           ; 3       ;
; counter60:counter60_2|out[6]           ; 3       ;
; counter60:counter60_1|out[6]           ; 3       ;
; counter60:counter60_2|reduce_nor~45    ; 2       ;
; counter60:counter60_1|out[4]           ; 2       ;
; counter60:counter60_1|reduce_nor~45    ; 2       ;
; counter60:counter60_1|out[7]           ; 2       ;
; counter24:counter24_1|reduce_nor~60    ; 2       ;
; counter24:counter24_1|reduce_nor~59    ; 2       ;
; counter24:counter24_1|reduce_nor~58    ; 2       ;
; counter24:counter24_1|reduce_nor~57    ; 2       ;
; counter24:counter24_1|out[4]           ; 2       ;
; counter60:counter60_2|out[4]           ; 2       ;
; chooser:chooser1|Select~745            ; 2       ;
; counter24:counter24_1|out[6]           ; 2       ;
; counter24:counter24_1|out[7]           ; 2       ;
; counter60:counter60_2|out[7]           ; 2       ;
; decoder:decoder1|out~57                ; 2       ;
; chooser:chooser1|i[0]~102              ; 1       ;
; counter24:counter24_1|add~191COUT1_195 ; 1       ;
; counter24:counter24_1|add~191          ; 1       ;
; counter24:counter24_1|add~189          ; 1       ;
; counter60:counter60_1|add~174COUT1_178 ; 1       ;
; counter60:counter60_1|add~174          ; 1       ;
; counter60:counter60_1|add~172          ; 1       ;
; counter60:counter60_2|add~174COUT1_178 ; 1       ;
; counter60:counter60_2|add~174          ; 1       ;
+----------------------------------------+---------+


+-----------------------------------------------------+
; Interconnect Usage Summary                          ;
+----------------------------+------------------------+
; Interconnect Resource Type ; Usage                  ;
+----------------------------+------------------------+
; C4s                        ; 48 / 8,840 ( < 1 % )   ;
; Direct links               ; 29 / 11,506 ( < 1 % )  ;
; Global clocks              ; 4 / 8 ( 50 % )         ;
; LAB clocks                 ; 13 / 156 ( 8 % )       ;
; LUT chains                 ; 1 / 2,619 ( < 1 % )    ;
; Local interconnects        ; 102 / 11,506 ( < 1 % ) ;
; M4K buffers                ; 0 / 468 ( 0 % )        ;
; R4s                        ; 32 / 7,520 ( < 1 % )   ;
+----------------------------+------------------------+


+---------------------------------------------------------------------------+
; LAB Logic Elements                                                        ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements  (Average = 5.14) ; Number of LABs  (Total = 14) ;
+--------------------------------------------+------------------------------+
; 1                                          ; 4                            ;
; 2                                          ; 2                            ;
; 3                                          ; 0                            ;
; 4                                          ; 2                            ;
; 5                                          ; 0                            ;
; 6                                          ; 1                            ;
; 7                                          ; 0                            ;
; 8                                          ; 0                            ;
; 9                                          ; 0                            ;
; 10                                         ; 5                            ;
+--------------------------------------------+------------------------------+


+-------------------------------------------------------------------+
; LAB-wide Signals                                                  ;
+------------------------------------+------------------------------+
; LAB-wide Signals  (Average = 1.57) ; Number of LABs  (Total = 14) ;
+------------------------------------+------------------------------+
; 1 Async. clear                     ; 6                            ;
; 1 Clock                            ; 7                            ;
; 1 Clock enable                     ; 5                            ;
; 2 Clocks                           ; 4                            ;
+------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Signals Sourced                                                        ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced  (Average = 5.64) ; Number of LABs  (Total = 14) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 4                            ;
; 2                                           ; 2                            ;
; 3                                           ; 0                            ;
; 4                                           ; 1                            ;
; 5                                           ; 1                            ;
; 6                                           ; 1                            ;
; 7                                           ; 0                            ;
; 8                                           ; 0                            ;
; 9                                           ; 0                            ;