counter60.v

来自「时钟发生器」· Verilog 代码 · 共 31 行

module	counter60 (
				clk,
				rst,
				carry,
				out);
input	clk,rst;
output	carry;
output	[7:0] out;

reg carry;
reg	[7:0] out;

always @ (posedge clk or negedge rst)
 begin
	if(!rst) begin
		carry<=0;
		out<=0;
	end
	else begin
		if(out==8'b0101_1001) begin
			out<=0;
			carry<=!carry;
		end
		else if(out[3:0]==4'b1001) begin
			out[7:4]<=out[7:4]+1;
			out[3:0]<=0;
		end
		else out[3:0]<=out[3:0]+1;
	end
end
endmodule