decoder.v

来自「时钟发生器」· Verilog 代码 · 共 21 行

module	decoder (
			in,
			out);
input [3:0] in;
output [7:0] out;

reg	[7:0] out;

always @ ( in )
 begin 
	case(in)
	0:out<=8'b1111_1100;
	1:out<=8'b0110_0000;
	2:out<=8'b1101_1010;
	3:out<=8'b1111_0010;
	4:out<=8'b0110_0110;
	5:out<=8'b1011_0110;
	default: out<=8'b1001_1110;//E :error
    endcase
end
endmodule