📄 counter24.rpt
字号:
p = Packed register
Device-Specific Information: f:\ahdldigital\counter24.rpt
counter24
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\ahdldigital\counter24.rpt
counter24
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 cp
Device-Specific Information: f:\ahdldigital\counter24.rpt
counter24
** EQUATIONS **
clr : INPUT;
cp : INPUT;
ec : INPUT;
s : INPUT;
-- Node name is 'bin0'
-- Equation name is 'bin0', type is output
bin0 = _LC1_A6;
-- Node name is 'bin1'
-- Equation name is 'bin1', type is output
bin1 = _LC3_A6;
-- Node name is 'bin2'
-- Equation name is 'bin2', type is output
bin2 = _LC6_A6;
-- Node name is 'bin3'
-- Equation name is 'bin3', type is output
bin3 = _LC8_A6;
-- Node name is 'bin4'
-- Equation name is 'bin4', type is output
bin4 = _LC4_A6;
-- Node name is 'bin5'
-- Equation name is 'bin5', type is output
bin5 = GND;
-- Node name is 'cy24'
-- Equation name is 'cy24', type is output
cy24 = _LC2_A6;
-- Node name is ':17' = 'q0'
-- Equation name is 'q0', location is LC7_A10, type is buried.
q0 = DFFE( _EQ001, GLOBAL( cp), VCC, VCC, VCC);
_EQ001 = !ec & !_LC5_A6 & q0
# ec & !_LC5_A6 & !q0;
-- Node name is ':16' = 'q1'
-- Equation name is 'q1', location is LC8_A10, type is buried.
q1 = DFFE( _EQ002, GLOBAL( cp), VCC, VCC, VCC);
_EQ002 = !_LC5_A6 & !q0 & q1
# ec & !_LC5_A6 & q0 & !q1
# !ec & !_LC5_A6 & q1;
-- Node name is ':15' = 'q2'
-- Equation name is 'q2', location is LC2_A10, type is buried.
q2 = DFFE( _EQ003, GLOBAL( cp), VCC, VCC, VCC);
_EQ003 = !_LC3_A10 & !_LC5_A6 & q2
# ec & _LC3_A10 & !_LC5_A6 & !q2
# !ec & !_LC5_A6 & q2;
-- Node name is ':14' = 'q3'
-- Equation name is 'q3', location is LC6_A10, type is buried.
q3 = DFFE( _EQ004, GLOBAL( cp), VCC, VCC, VCC);
_EQ004 = !_LC4_A10 & !_LC5_A6 & q3
# ec & _LC4_A10 & !_LC5_A6 & !q3
# !ec & !_LC5_A6 & q3;
-- Node name is ':13' = 'q4'
-- Equation name is 'q4', location is LC1_A10, type is buried.
q4 = DFFE( _EQ005, GLOBAL( cp), VCC, VCC, VCC);
_EQ005 = !_LC5_A6 & !_LC5_A10 & q4
# ec & !_LC5_A6 & _LC5_A10 & !q4
# !ec & !_LC5_A6 & q4;
-- Node name is '|LPM_ADD_SUB:78|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A10', type is buried
_LC3_A10 = LCELL( _EQ006);
_EQ006 = q0 & q1;
-- Node name is '|LPM_ADD_SUB:78|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A10', type is buried
_LC4_A10 = LCELL( _EQ007);
_EQ007 = q0 & q1 & q2;
-- Node name is '|LPM_ADD_SUB:78|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A10', type is buried
_LC5_A10 = LCELL( _EQ008);
_EQ008 = q0 & q1 & q2 & q3;
-- Node name is ':51'
-- Equation name is '_LC5_A6', type is buried
!_LC5_A6 = _LC5_A6~NOT;
_LC5_A6~NOT = LCELL( _EQ009);
_EQ009 = !clr & !_LC2_A6;
-- Node name is '~216~1'
-- Equation name is '~216~1', location is LC7_A6, type is buried.
-- synthesized logic cell
_LC7_A6 = LCELL( _EQ010);
_EQ010 = q2
# !q4
# q1;
-- Node name is ':216'
-- Equation name is '_LC2_A6', type is buried
!_LC2_A6 = _LC2_A6~NOT;
_LC2_A6~NOT = LCELL( _EQ011);
_EQ011 = q0
# !q3
# _LC7_A6;
-- Node name is ':264'
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = LCELL( _EQ012);
_EQ012 = q4 & s;
-- Node name is ':270'
-- Equation name is '_LC8_A6', type is buried
_LC8_A6 = LCELL( _EQ013);
_EQ013 = q3 & s;
-- Node name is ':276'
-- Equation name is '_LC6_A6', type is buried
_LC6_A6 = LCELL( _EQ014);
_EQ014 = q2 & s;
-- Node name is ':282'
-- Equation name is '_LC3_A6', type is buried
_LC3_A6 = LCELL( _EQ015);
_EQ015 = q1 & s;
-- Node name is ':288'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = LCELL( _EQ016);
_EQ016 = q0 & s;
Project Information f:\ahdldigital\counter24.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,586K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -