📄 hen.rpt
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Device-Specific Information: f:\ahdldigital\hen.rpt
hen
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 1/ 48( 2%) 2/ 48( 4%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
B: 3/ 96( 3%) 4/ 48( 8%) 2/ 48( 4%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
C: 7/ 96( 7%) 1/ 48( 2%) 1/ 48( 2%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\ahdldigital\hen.rpt
hen
** EQUATIONS **
seg10 : INPUT;
seg11 : INPUT;
seg12 : INPUT;
seg13 : INPUT;
seg14 : INPUT;
seg15 : INPUT;
seg16 : INPUT;
seg17 : INPUT;
seg20 : INPUT;
seg21 : INPUT;
seg22 : INPUT;
seg23 : INPUT;
seg24 : INPUT;
seg25 : INPUT;
seg26 : INPUT;
seg27 : INPUT;
-- Node name is 'seg1out0~1'
-- Equation name is 'seg1out0~1', location is LC1_A2, type is buried.
-- synthesized logic cell
_LC1_A2 = LCELL( seg10);
-- Node name is 'seg1out0'
-- Equation name is 'seg1out0', type is output
seg1out0 = _LC1_A2;
-- Node name is 'seg1out1~1'
-- Equation name is 'seg1out1~1', location is LC8_C20, type is buried.
-- synthesized logic cell
_LC8_C20 = LCELL( seg11);
-- Node name is 'seg1out1'
-- Equation name is 'seg1out1', type is output
seg1out1 = _LC8_C20;
-- Node name is 'seg1out2~1'
-- Equation name is 'seg1out2~1', location is LC8_A16, type is buried.
-- synthesized logic cell
_LC8_A16 = LCELL( seg12);
-- Node name is 'seg1out2'
-- Equation name is 'seg1out2', type is output
seg1out2 = _LC8_A16;
-- Node name is 'seg1out3~1'
-- Equation name is 'seg1out3~1', location is LC4_A13, type is buried.
-- synthesized logic cell
_LC4_A13 = LCELL( seg13);
-- Node name is 'seg1out3'
-- Equation name is 'seg1out3', type is output
seg1out3 = _LC4_A13;
-- Node name is 'seg1out4~1'
-- Equation name is 'seg1out4~1', location is LC7_C9, type is buried.
-- synthesized logic cell
_LC7_C9 = LCELL( seg14);
-- Node name is 'seg1out4'
-- Equation name is 'seg1out4', type is output
seg1out4 = _LC7_C9;
-- Node name is 'seg1out5~1'
-- Equation name is 'seg1out5~1', location is LC4_C23, type is buried.
-- synthesized logic cell
_LC4_C23 = LCELL( seg15);
-- Node name is 'seg1out5'
-- Equation name is 'seg1out5', type is output
seg1out5 = _LC4_C23;
-- Node name is 'seg1out6~1'
-- Equation name is 'seg1out6~1', location is LC5_C11, type is buried.
-- synthesized logic cell
_LC5_C11 = LCELL( seg16);
-- Node name is 'seg1out6'
-- Equation name is 'seg1out6', type is output
seg1out6 = _LC5_C11;
-- Node name is 'seg1out7~1'
-- Equation name is 'seg1out7~1', location is LC1_B5, type is buried.
-- synthesized logic cell
_LC1_B5 = LCELL( seg17);
-- Node name is 'seg1out7'
-- Equation name is 'seg1out7', type is output
seg1out7 = _LC1_B5;
-- Node name is 'seg2out0~1'
-- Equation name is 'seg2out0~1', location is LC8_B1, type is buried.
-- synthesized logic cell
_LC8_B1 = LCELL( seg20);
-- Node name is 'seg2out0'
-- Equation name is 'seg2out0', type is output
seg2out0 = _LC8_B1;
-- Node name is 'seg2out1~1'
-- Equation name is 'seg2out1~1', location is LC7_A24, type is buried.
-- synthesized logic cell
_LC7_A24 = LCELL( seg21);
-- Node name is 'seg2out1'
-- Equation name is 'seg2out1', type is output
seg2out1 = _LC7_A24;
-- Node name is 'seg2out2~1'
-- Equation name is 'seg2out2~1', location is LC6_B2, type is buried.
-- synthesized logic cell
_LC6_B2 = LCELL( seg22);
-- Node name is 'seg2out2'
-- Equation name is 'seg2out2', type is output
seg2out2 = _LC6_B2;
-- Node name is 'seg2out3~1'
-- Equation name is 'seg2out3~1', location is LC2_B9, type is buried.
-- synthesized logic cell
_LC2_B9 = LCELL( seg23);
-- Node name is 'seg2out3'
-- Equation name is 'seg2out3', type is output
seg2out3 = _LC2_B9;
-- Node name is 'seg2out4~1'
-- Equation name is 'seg2out4~1', location is LC1_B24, type is buried.
-- synthesized logic cell
_LC1_B24 = LCELL( seg24);
-- Node name is 'seg2out4'
-- Equation name is 'seg2out4', type is output
seg2out4 = _LC1_B24;
-- Node name is 'seg2out5~1'
-- Equation name is 'seg2out5~1', location is LC4_B11, type is buried.
-- synthesized logic cell
_LC4_B11 = LCELL( seg25);
-- Node name is 'seg2out5'
-- Equation name is 'seg2out5', type is output
seg2out5 = _LC4_B11;
-- Node name is 'seg2out6~1'
-- Equation name is 'seg2out6~1', location is LC1_C19, type is buried.
-- synthesized logic cell
_LC1_C19 = LCELL( seg26);
-- Node name is 'seg2out6'
-- Equation name is 'seg2out6', type is output
seg2out6 = _LC1_C19;
-- Node name is 'seg2out7~1'
-- Equation name is 'seg2out7~1', location is LC2_B16, type is buried.
-- synthesized logic cell
_LC2_B16 = LCELL( seg27);
-- Node name is 'seg2out7'
-- Equation name is 'seg2out7', type is output
seg2out7 = _LC2_B16;
Project Information f:\ahdldigital\hen.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,319K
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