📄 kk.rpt
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- 5 - A 20 OR2 ! 0 4 0 1 |TIMER_SET:1|:3634
- 6 - A 20 OR2 ! 0 4 0 1 |TIMER_SET:1|:3640
- 7 - A 20 OR2 ! 0 4 0 1 |TIMER_SET:1|:3646
- 8 - A 20 OR2 ! 0 4 0 1 |TIMER_SET:1|:3652
- 2 - A 20 OR2 ! 0 4 0 1 |TIMER_SET:1|:3658
- 4 - A 01 OR2 ! 0 3 0 1 |TIMER_SET:1|:3670
- 6 - A 13 OR2 ! 0 3 0 1 |TIMER_SET:1|:3682
- 7 - A 13 OR2 ! 0 4 0 1 |TIMER_SET:1|:3688
- 8 - A 13 OR2 ! 0 4 0 1 |TIMER_SET:1|:3694
- 2 - A 13 OR2 ! 0 4 0 8 |TIMER_SET:1|:3700
- 2 - A 15 OR2 0 4 0 1 |TIMER_SET:1|:3704
- 4 - A 13 OR2 0 4 0 1 |TIMER_SET:1|:3706
- 4 - A 15 OR2 0 4 0 1 |TIMER_SET:1|:3710
- 3 - A 15 OR2 0 4 0 1 |TIMER_SET:1|:3712
- 6 - A 15 OR2 0 4 0 1 |TIMER_SET:1|:3716
- 5 - A 15 OR2 0 4 0 1 |TIMER_SET:1|:3718
- 8 - A 15 OR2 0 4 0 1 |TIMER_SET:1|:3722
- 7 - A 15 OR2 0 4 0 1 |TIMER_SET:1|:3724
- 1 - A 15 OR2 0 4 0 3 |TIMER_SET:1|:3730
- 3 - A 09 OR2 ! 0 3 0 5 |TIMER_SET:1|:3770
- 1 - A 11 OR2 s ! 0 4 0 1 |TIMER_SET:1|~3797~1
- 4 - A 06 OR2 ! 0 4 0 13 |TIMER_SET:1|:3797
- 6 - A 11 OR2 s 0 4 0 1 |TIMER_SET:1|~3802~1
- 2 - A 11 AND2 0 4 0 9 |TIMER_SET:1|:3802
- 1 - A 06 OR2 s 0 4 0 1 |TIMER_SET:1|~3803~1
- 2 - A 14 OR2 s 0 4 0 3 |TIMER_SET:1|~3804~1
- 3 - A 02 OR2 s 0 2 0 2 |TIMER_SET:1|~3804~2
- 4 - A 11 OR2 ! 0 4 0 9 |TIMER_SET:1|:3808
- 2 - A 06 OR2 s ! 0 4 0 1 |TIMER_SET:1|~3809~1
- 5 - A 11 OR2 s ! 0 3 0 1 |TIMER_SET:1|~3810~1
- 6 - B 11 OR2 s ! 0 4 0 1 |TIMER_SET:1|~3814~1
- 2 - B 02 OR2 s ! 0 3 0 2 |TIMER_SET:1|~3814~2
- 7 - B 11 OR2 s ! 0 3 0 1 |TIMER_SET:1|~3814~3
- 4 - B 11 OR2 s ! 0 4 0 1 |TIMER_SET:1|~3814~4
- 3 - B 03 AND2 s 0 3 0 2 |TIMER_SET:1|~3814~5
- 4 - B 03 OR2 s ! 0 4 0 1 |TIMER_SET:1|~3814~6
- 6 - B 07 AND2 s ! 0 3 0 1 |TIMER_SET:1|~3814~7
- 2 - B 11 OR2 s ! 0 3 0 1 |TIMER_SET:1|~3814~8
- 1 - B 07 OR2 s ! 0 4 0 1 |TIMER_SET:1|~3814~9
- 1 - B 11 OR2 s ! 0 4 0 1 |TIMER_SET:1|~3814~10
- 5 - B 03 OR2 s ! 0 4 0 1 |TIMER_SET:1|~3814~11
- 6 - B 03 OR2 s ! 0 3 0 1 |TIMER_SET:1|~3814~12
- 1 - B 03 OR2 s ! 0 4 0 1 |TIMER_SET:1|~3814~13
- 6 - A 02 OR2 s ! 0 4 0 1 |TIMER_SET:1|~3814~14
- 7 - A 02 AND2 s ! 0 3 0 1 |TIMER_SET:1|~3814~15
- 2 - A 02 OR2 0 4 0 9 |TIMER_SET:1|:3814
- 2 - B 07 OR2 s ! 0 4 0 1 |TIMER_SET:1|~3816~1
- 6 - B 02 OR2 s 0 3 0 3 |TIMER_SET:1|~3816~2
- 8 - B 07 OR2 s ! 0 3 0 1 |TIMER_SET:1|~3816~3
- 7 - B 03 OR2 s ! 0 4 0 1 |TIMER_SET:1|~3816~4
- 2 - A 09 OR2 s 0 3 0 5 |TIMER_SET:1|~3816~5
- 5 - A 06 AND2 s ! 0 4 0 2 |TIMER_SET:1|~3816~6
- 5 - D 22 AND2 0 4 0 6 |TIMER_SET:1|:3833
- 6 - D 22 OR2 ! 0 4 0 6 |TIMER_SET:1|:3838
- 3 - D 17 AND2 s 0 3 0 1 |TIMER_SET:1|~3843~1
- 1 - D 22 AND2 0 4 0 3 |TIMER_SET:1|:3843
- 3 - D 22 AND2 0 4 0 2 |TIMER_SET:1|:3848
- 7 - D 22 OR2 ! 0 4 0 5 |TIMER_SET:1|:3853
- 8 - D 22 AND2 0 4 0 6 |TIMER_SET:1|:3868
- 6 - A 05 OR2 s ! 0 3 0 1 |TIMER_SET:1|~3873~1
- 6 - D 20 AND2 0 2 0 4 |TIMER_SET:1|:3883
- 1 - A 05 OR2 s ! 0 3 0 6 |TIMER_SET:1|~3888~1
- 2 - D 17 AND2 s ! 0 2 0 5 |TIMER_SET:1|~3893~1
- 7 - D 20 AND2 0 3 0 2 |TIMER_SET:1|:3893
- 4 - D 20 OR2 ! 0 3 0 3 |TIMER_SET:1|:3898
- 1 - D 20 OR2 0 3 0 1 |TIMER_SET:1|:3948
- 3 - D 18 OR2 s 0 3 0 2 |TIMER_SET:1|~4000~1
- 8 - D 18 OR2 s 0 4 0 1 |TIMER_SET:1|~4000~2
- 8 - D 20 AND2 0 2 0 2 |TIMER_SET:1|:4021
- 7 - A 05 AND2 s 0 3 0 4 |TIMER_SET:1|~4039~1
- 6 - D 18 OR2 s 0 4 0 2 |TIMER_SET:1|~4039~2
- 7 - D 18 OR2 0 4 0 1 |TIMER_SET:1|:4051
- 4 - D 16 AND2 s 0 2 0 1 |TIMER_SET:1|~4065~1
- 4 - D 17 OR2 0 2 0 1 |TIMER_SET:1|:4084
- 5 - D 17 OR2 0 4 0 1 |TIMER_SET:1|:4098
- 6 - D 17 OR2 0 4 0 1 |TIMER_SET:1|:4108
- 2 - D 22 OR2 s 0 4 0 1 |TIMER_SET:1|~4110~1
- 3 - D 20 OR2 0 4 0 1 |TIMER_SET:1|:4132
- 8 - D 14 OR2 0 4 0 1 |TIMER_SET:1|:4149
- 2 - D 14 OR2 0 4 0 1 |TIMER_SET:1|:4159
- 4 - D 18 OR2 s 0 2 0 1 |TIMER_SET:1|~4207~1
- 1 - D 18 OR2 0 4 0 1 |TIMER_SET:1|:4207
- 5 - D 14 OR2 s 0 3 0 1 |TIMER_SET:1|~4246~1
- 3 - D 14 OR2 0 4 0 2 |TIMER_SET:1|:4246
- 7 - D 14 OR2 s 0 4 0 1 |TIMER_SET:1|~4267~1
- 2 - D 20 OR2 0 3 0 2 |TIMER_SET:1|:4282
- 4 - D 22 OR2 s 0 4 0 5 |TIMER_SET:1|~4303~1
- 5 - D 20 OR2 s 0 4 0 1 |TIMER_SET:1|~4303~2
- 5 - D 16 OR2 s 0 2 0 4 |TIMER_SET:1|~4312~1
- 6 - D 14 OR2 0 4 0 1 |TIMER_SET:1|:4312
- 1 - E 12 OR2 ! 0 2 0 1 |TIMER_SET:1|:4321
- 5 - B 05 OR2 ! 0 3 0 3 |TIMER_SET:1|:4328
- 6 - E 11 OR2 ! 1 2 0 3 |TIMER_SET:1|:4346
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\max+plusii learning\course and others\vhdl\kk.rpt
kk
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 51/ 96( 53%) 31/ 48( 64%) 11/ 48( 22%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 15/ 96( 15%) 36/ 48( 75%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 17/ 96( 17%) 2/ 48( 4%) 18/ 48( 37%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
E: 2/ 96( 2%) 2/ 48( 4%) 0/ 48( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 9/24( 37%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\max+plusii learning\course and others\vhdl\kk.rpt
kk
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 52 cp
Device-Specific Information:e:\max+plusii learning\course and others\vhdl\kk.rpt
kk
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 7 |TIMER_SET:1|counter60:u1|:180
LCELL 7 |TIMER_SET:1|counter60:u2|:180
LCELL 3 |TIMER_SET:1|:4328
Device-Specific Information:e:\max+plusii learning\course and others\vhdl\kk.rpt
kk
** EQUATIONS **
cp : INPUT;
key0 : INPUT;
key1 : INPUT;
key2 : INPUT;
-- Node name is 'segout0'
-- Equation name is 'segout0', type is output
segout0 = _LC4_D14;
-- Node name is 'segout1'
-- Equation name is 'segout1', type is output
segout1 = _LC1_D14;
-- Node name is 'segout2'
-- Equation name is 'segout2', type is output
segout2 = _LC2_D16;
-- Node name is 'segout3'
-- Equation name is 'segout3', type is output
segout3 = _LC1_D16;
-- Node name is 'segout4'
-- Equation name is 'segout4', type is output
segout4 = _LC1_D17;
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